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description the M37736MHBXXXGP is a single-chip microcomputer using the 7700 family core. this single-chip microcomputer has a cpu and a bus interface unit. the cpu is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. this microcomputer also includes a 32 khz oscillation circuit, in addition to the rom, ram, multiple-function timers, serial i/o, a-d converter, and others. in the M37736MHBXXXGP, as the multiplex method of the external bus, either of 2 types can be selected. features l number of basic instructions .................................................. 103 l memory size rom ............................................... 124 kbytes ram ................................................ 3968 bytes l instruction execution time the fastest instruction at 25 mhz frequency ...................... 160 ns l single power supply ...................................................... 5 v 10% l low power dissipation (at 25 mhz frequency) ............................................47.5 mw (typ.) l interrupts ............................................................ 19 types, 7 levels l multiple-function 16-bit timer ................................................. 5 + 3 l serial i/o (uart or clock synchronous) ..................................... 3 l 10-bit a-d converter ............................................ 8-channel inputs l 12-bit watchdog timer l programmable input/output, output (ports p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10)..........................84 l clock generating circuit ........................................ 2 circuits built-in l package .........................................................................100-pin qfp application control devices for general commercial equipment such as office automation, office equipment, and others. control devices for general industrial equipment such as communication equipment, and others. pin configuration (top view) mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 1 preliminary notice: this is not a final specification. some parametric limits are subject to change. 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 ? p2 3 /a 19 /a 3 /d 3 ? p2 4 /a 20 /a 4 /d 4 ? p2 5 /a 21 /a 5 /d 5 ? p2 6 /a 22 /a 6 /d 6 ? p2 7 /a 23 /a 7 /d 7 ? p3 0 /r/w/wel ? p3 1 /bhe/weh ? p3 2 /ale ? p3 3 /hlda ? evl0 ? evl1 M37736MHBXXXGP v cc v ss ? e/rde ? x out ? x in ? reset ? bsel ? cnv ss ? byte ? p4 0 /hold ? p4 1 /rdy 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p8 6 /r x d 1 ? p8 5 /clk 1 ? p8 4 /cts 1 /rts 1 ? p8 3 /t x d 0 ? p8 2 /r x d 0 /clks 0 ? p8 1 /clk 0 ? p8 0 /cts 0 /rts 0 /clks 1 ? v cc av cc v ref ? av ss v ss p7 7 /an 7 /x cin ? p7 6 /an 6 /x cout ? p7 5 /an 5 /ad trg ? p7 4 /an 4 ? p7 3 /an 3 ? p7 2 /an 2 ? p7 1 /an 1 ? p7 0 /an 0 ? 75 74 73 72 71 80 79 78 77 76 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ? p9 2 /r x d 2 ? p9 3 /t x d 2 ? p9 4 ? p8 7 /t x d 1 ? p9 0 /cts 2 ? p9 1 /clk 2 ? p9 5 ? p9 6 ? p9 7 ? p0 0 /a 0 /cs 0 ? p0 1 /a 1 /cs 1 ? p0 2 /a 2 /cs 2 ? p0 3 /a 3 /cs 3 ? p0 4 /a 4 /cs 4 ? p0 5 /a 5 /rsmp ? p0 6 /a 6 /a 16 ? p0 7 /a 7 /a 17 ? p1 0 /a 8 /d 8 ? p1 1 /a 9 /d 9 ? p1 2 /a 10 /d 10 ? p1 3 /a 11 /d 11 ? p1 4 /a 12 /d 12 ? p1 5 /a 13 /d 13 ? p1 6 /a 14 /d 14 ? p1 7 /a 15 /d 15 ? p2 0 /a 16 /a 0 /d 0 ? p2 1 /a 17 /a 1 /d 1 ? p2 2 /a 18 /a 2 /d 2 p6 5 /tb0 in ? p6 7 /tb2 in / f sub ? p6 6 /tb1 in ? p6 4 /int 2 ? p6 3 /int 1 ? p6 2 /int 0 ? p6 1 /ta4 in ? p6 0 /ta4 out ? p5 7 /ta3 in ? p5 6 /ta3 out ? p5 5 /ta2 in ? p5 4 /ta2 out ? p5 3 /ta1 in ? p5 2 /ta1 out ? p5 1 /ta0 in ? p5 0 /ta0 out ? p10 7 /ki 3 ? p10 6 /ki 2 ? p10 5 /ki 1 ? p10 4 /ki 0 ? p10 3 ? p10 2 ? p10 1 ? p10 0 ? p4 7 ? p4 6 ? p4 5 ? 26 27 28 29 30 p4 4 ? p4 3 ? p4 2 / f 1 ? outline 100p6s-a
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 2 M37736MHBXXXGP block diagram ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? clock input x in clock output x out clock generating circuit timer ta4(16) ram 3968 bytes rom 124 kbytes timer ta3(16) timer ta2(16) timer ta1(16) p8(8) input/output port p8 p7(8) input/output port p7 x cin x cout p6(8) input/output port p6 p5(8) input/output port p5 p4(8) input/output port p4 p3(4) input/output port p3 p2(8) input/output port p2 p1(8) input/output port p1 p0(8) input/output port p0 timer ta0(16) watchdog timer timer tb2(16) timer tb1(16) timer tb0(16) uart2(9) uart1(9) uart0(9) a-d converter(10) instruction register(8) data buffer db h (8) data buffer db l (8) processor status register ps(11) direct page register dpr(16) stack pointer s(16) index register y(16) index register x(16) accumulator b(16) arithmetic logic unit(16) accumulator a(16) instruction queue buffer q 0 (8) instruction queue buffer q 1 (8) incrementer(24) program address register pa(24) data address register da(24) instruction queue buffer q 2 (8) program counter pc(16) incrementer/decrementer(24) program bank register pg(8) data bank register dt((8) input buffer register ib(16) address bus data bus(even) data bus(odd) x cin x cout enable output e reset input reset (0v) v ss (0v) av ss cnv ss av cc reference voltage input v ref bus method selection input bsel external data bus width selection input byte v cc ? ? ? ? ? ? ? ? ? p9(8) output port p9 ? ? ? ? ? ? ? ? ? p10(8) input/output port p10
3 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer functions of M37736MHBXXXGP memory size input/output ports multi-function timers interrupts clock generating circuit input/output characteristic memory expansion parameter functions number of basic instructions 103 instruction execution time 160 ns (the fastest instruction at external clock 25 mhz frequency) rom 124 kbytes ram 3968 bytes p0 C p2, p4 C p8, p10 8-bit 5 9 p3 4-bit 5 1 output port p9 8-bit 5 1 ta0, ta1, ta2, ta3, ta4 16-bit 5 5 tb0, tb1, tb2 16-bit 5 3 serial i/o (uart or clock synchronous serial i/o) 5 3 a-d converter 10-bit 5 1 (8 channels) watchdog timer 12-bit 5 1 3 external types, 16 internal types each interrupt can be set to the priority level (0 C 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) supply voltage 5 v 10% power dissipation 47.5 mw (at external clock 25 mhz frequency) input/output voltage 5 v output current 5 ma external bus mode a; maximum 16 mbytes, external bus mode b; maximum 1 mbytes operating temperature range C20 to 85 c device structure cmos high-performance silicon gate process package 100-pin plastic molded qfp (100p6s-a)
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 4 pin name input/output functions vcc, power source apply 5 v 10% to vcc and 0 v to vss. vss cnvss cnvss input input this pin controls the processor mode. connect to vss for the single-chip mode and the memory expansion mode, and to vcc for the microprocessor mode. _____ reset reset input input when l level is applied to this pin, the microcomputer ent ers the reset state. these are pins of main-clock generating circuit. connect a c eramic resonator or a quartz- crystal oscillator between x in and x out . when an external clock is used, the clock source should be connected to the x in pin, and the x out pin should be left open. _ e enable output output this pin functions as the enable signal output pin which ind icates the access status in the internal bus. in the external bus mode b and the memory expansion mod e or the microprocessor mode, ___ this pin output signal rde . byte external data input in the memory expansion mode or the microprocessor mode, thi s pin determines whether the bus width external data bus has an 8-bit width or a 16-bit width. the data bus has a 16-bit width when l selection input signal is input and an 8-bit width when h signal is input. bsel input in the memory expansion mode or the microprocessor mode, thi s pin determines the external bus mode. the bus mode becomes the external bus mode a when h signal is input, and the external bus mode b when l signal is input. avcc, analog power power source input pin for the a-d converter. externally con nect avcc to vcc and avss to vss. avss source input v ref reference input this is reference voltage input pin for the a-d converter. voltage input p0 0 C p0 7 i/o port p0 i/o in the single-chip mode, port p0 becomes an 8-bit i/o port. an i/o direction register is available so that each pin can be programmed for input or output. these p orts are in the input mode when reset. in the memory expansion mode or the microprocessor mode, the se pins output address (a 0 C a 7 ) ___ ___ ____ at the external bus mode a, and these pins output signals cs 0 C cs 4 and rsmp, and addresses (a 16 , a 17 ) at the external bus mode b. p1 0 C p1 7 i/o port p1 i/o in the single-chip mode, these pins have the same functions as port p0. when the byte pin is set to l in the memory expansion mode or the microprocessor mo de and external data bus has a 16-bit width, high-order data (d 8 C d 15 ) is input/output or an address (a 8 C a 15 ) is output. when the byte pin is h and an external data bus has an 8-bit wi dth, only address (a 8 C a 15 ) is output. p2 0 C p2 7 i/o port p2 i/o in the single-chip mode, these pins have the same functions as port p0. in the memory expansion mode or the microprocessor mode, low-order data (d 0 C d 7 ) is input/output or an address is output. when using the external bus mode a, the address is a 16 C a 23 . when using the external bus mode b, the address is a 0 C a 7 . p3 0 C p3 3 i/o port p3 i/o in the single-chip mode, these pins have the same function a s port p0. in the memory expansion __ ___ ____ mode or the microprocessor mode, r/ w , bhe , ale, and hlda signals are output at the external ___ ___ ____ bus mode a, and wel , weh , ale, and hlda signals are output at the external bus mode b. p4 0 C p4 7 i/o port p4 i/o in the single-chip mode, these pins have the same functions as port p0. in the memory expansion ____ ___ mode or the microprocessor mode, p4 0 , p4 1 and p4 2 become hold and rdy input pins, and a clock 1 output pin, respectively. functions of the other pins are t he same as in the single-chip mode. however, in the memory expansion mode, p4 2 can be selected as an i/o port. p5 0 C p5 7 i/o port p5 i/o in addition to having the same functions as port p0 in the s ingle-chip mode, these pins also function as i/o pins for timers a0 to a3. p6 0 C p6 7 i/o port p6 i/o in addition to having the same functions as port p0 in the s ingle-chip mode, these pins also ___ ___ function as i/o pins for timer a4, input pins for external i nterrupt input ( int 0 C int 2 ) and input pins for timers b0 to b2. p6 7 also functions as sub-clock sub output pin. p7 0 C p7 7 i/o port p7 i/o in addition to having the same functions as port p0 in the s ingle-chip mode, these pins function as input pins for a-d converter. additionally, p7 6 and p7 7 have the function as the output pin (x cout ) and the input pin (x cin ) of the sub-clock (32 khz) oscillation circuit, respectivel y. when p7 6 and p7 7 are used as the x cout and x cin pins, connect a resonator or an oscillator between the bot h. p8 0 C p8 7 i/o port p8 i/o in addition to having the same functions as port p0 in the s ingle-chip mode, these pins also function as i/o pins for uart 0 and uart 1. p9 0 C p9 7 output port p9 output port p9 is an 8-bit i/o port. these ports are floating when reset. when writting to the port latch, these ports become the output mode. p9 0 C p9 3 also function as i/o port for uart 2. p10 0 C p10 7 i/o port p10 i/o in addition to having the same functions as port p0 in the s ingle-chip mode, p10 4 C p10 7 also __ __ function as input pins for key input interrupt input ( ki 0 C ki 3 ). output these pins should be left open. pin description x in clock input input bus method select input x out clock output output evl0, evl1 CC
5 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer basic function blocks the M37736MHBXXXGP contains the following peripheral devices on a single chip: rom, ram, cpu, bus interface unit, timers, serial i/o, a-d converter, i/o ports, clock generating circuit and others. each of these devices is described below. memory the memory map is shown in figure 1. the address space has a capacity of 16 mbytes and is allocated to addresses from 0 16 to ffffff 16 . the address space is divided by 64-kbyte unit called bank. the banks are numbered from 0 16 to ff 16 . however, in the external bus mode b, banks 10 16 to ff 16 cannot be accessed. built-in rom, ram and control registers for internal peripheral devices are assigned to banks 0 16 and 1 16 . the 124-kbyte area from addresses 1000 16 to 1ffff 16 is the built-in rom. addresses ffd6 16 to ffff 16 are the reset and interrupt vector addresses and contain the interrupt vectors. refer to the section on interrupts for details. the 3968-byte area allocated to addresses from 80 16 to fff 16 is the built-in ram. in addition to storing data, the ram is used as stack during a subroutine call or interrupts. peripheral devices such as i/o ports, a-d converter, serial i/o, timer, and interrupt control registers are allocated to addresses from 0 16 to 7f 16 . additionally, the internal rom and ram area can be modified by software. refer to the section on rom area modification function for details. a 256-byte direct page area can be allocated anywhere in bank 0 16 by using the direct page register (dpr). in the direct page addressing mode, the memory in the direct page area can be accessed with two words. hence program steps can be reduced. fig. 1 memory map a-d/uart2 trans./rece. timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 0 watchdog timer dbc brk instruction zero divide reset internal peripheral devices control registers refer to fig. 2 for detail information interrupt vector table 000000 16 00ffff 16 010000 16 01ffff 16 bank 0 16 bank 1 16 fe0000 16 feffff 16 ff0000 16 ffffff 16 bank ff 16 bank fe 16 01ffff 16 00ffd6 16 000fff 16 000000 16 00007f 16 000080 16 internal ram 3968 bytes internal rom 124 kbytes 00fffe 16 00ffd6 16 00007f 16 000000 16 uart1 transmission uart1 receive uart0 transmission uart0 receive ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int 1 001000 16 00ffff 16 notes 1. internal rom and ram area can be modified. (refer to the section on rom area modification function.) 2. in the external bus mode b, banks 10 16 to ff 16 cannot be accessed.
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 6 fig. 2 location of internal peripheral devices and interrupt control registers 00002a uart 0 transmission interrupt control register uart 1 transmission interrupt control register int 2 /key input interrupt control register port p1 direction register uart 0 transmit/receive mode register uart 0 baud rate register (brg0) uart 0 transmit/receive control register 0 uart 0 transmit/receive control register 1 uart 0 transmission buffer register uart 1 transmit/receive control register 0 uart 1 transmit/receive mode register uart 1 baud rate register (brg1) uart 1 transmit/receive control register 1 uart 0 receive buffer register uart 1 transmission buffer register uart 1 receive buffer register port p0 register a-d register 0 a-d register 2 port p1 register port p0 direction register port p2 register port p3 register port p4 register port p5 register port p6 register port p7 register port p8 register a-d control register 0 a-d control register 1 a-d register 1 a-d register 3 a-d register 4 a-d register 5 000000 000001 000002 000003 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001a 00001b 00001c 00001d 00001e 00001f 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002b 00002c 00002d 00002e 00002f 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003a 00003b 00003c 00003d 00003e 00003f 00000b 00000c 00000d 00000e 00000f 00000a 000004 000040 000041 000042 000043 000045 000046 000047 000048 000049 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005a 00005b 00005c 00005d 00005e 00005f 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006a 00006b 00006c 00006d 00006e 00006f 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007a 00007b 00007c 00007d 00007e 00007f 00004b 00004c 00004d 00004e 00004f 00004a 000044 address (hexadecimal notation) address (hexadecimal notation) timer a1 register timer a4 register timer a2 register timer a3 register timer b0 register timer b1 register timer b2 register count start flag one-shot start flag up-down flag timer a0 register timer a0 mode register timer a1 mode register timer a2 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 watchdog timer register watchdog timer frequency selection flag a-d/uart 2 trans./rece. interrupt control register uart 0 receive interrupt control register uart 1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register processor mode register 1 oscillation circuit control register 1 serial transmit control register port function control register oscillation circuit control register 0 timer a3 mode register port p2 direction register port p3 direction register port p4 direction register port p5 direction register port p6 direction register port p7 direction register port p8 direction register reserved area (note) a-d register 6 a-d register 7 uart 2 transmit/receive control register 1 uart 2 transmit/receive control register 0 uart 2 transmission buffer register uart 2 baud rate register (brg2) uart 2 transmit/receive mode register memory allocation control register reserved area (note) uart 2 receive buffer register note. do not write to this address. port p9 register port p10 register port p10 direction register reserved area (note)
7 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer central processing unit (cpu) the cpu has ten registers and is shown in figure 3. each of these registers is described below. accumulator a (a) accumulator a is the main register of the microcomputer. it consists of 16 bits and the low-order 8 bits can be used separately. the data length flag (m) determines whether the register is used as a 16-bit register or as an 8-bit register. it is used as a 16-bit register when flag m is 0 and as an 8-bit register when flag m is 1. flag m is a part of the processor status register (ps) which is described later. data operations such as arithmetic operation, data transfer, input/ output, etc., are executed mainly through the accumulator a. accumulator b (b) accumulator b has the same functions as accumulator a, but the use of accumulator b requires more instruction bytes and execution cycles than accumulator a. index register x (x) index register x consists of 16 bits and the low-order 8 bits can be used separately. the index register length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. it is used as a 16-bit register when flag x is 0 and as an 8-bit register when flag x is 1. flag x is a part of the processor status register (ps) which is described later. in an index addressing mode where register x is used as the index register, the contents of this address is added to obtain the real address. also, when executing a block transfer instruction (mvp, mvn), the contents of index register x indicates the low-order 16 bits of the source data address. the third byte of the mvp or mvn is the high- order 8 bits of the source data address. index register y (y) index register y consists of 16 bits and the low-order 8 bits can be used separately. the index register length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. it is used as a 16-bit register when flag x is 0 and as an 8-bit register when flag x is 1. flag x is a part of the processor status register (ps) which is described later. in an index addressing mode where register y is used as the index register, the contents of this address is added to obtain the real address. also, when executing a block transfer instruction (mvp, mvn), the contents of index register y indicates the low-order 16 bits of the destination data address. the second byte of the mvp or mvn is the high-order 8 bits of the destination data address. fig. 3 register structure 70 pg program bank register (pg) 70 dt data bank register (dt) carry flag zero frag interrupt disable flag decimal mode flag index register length flag data length flag negative flag overflow flag processor interrupt priority level (ipl) accumulator a (a) accumulator b (b) index register x (x) index register y (y) stack pointer (s) program counter (pc) direct page register (dpr) processor status register (ps) 0 a h a l 15 0 7 b h b l 15 0 7 x h x l 15 0 7 y h y l 15 0 7 15 0 pc 15 0 15 0 dpr 7 15 0 n ipl 2 ipl 0 ipl 1 c z i d x m v 00 00 s
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 8 stack pointer (s) stack pointer (s) is a 16-bit register. it is used during a subroutine call or interrupts. it is also used during stack, stack pointer relative, or stack pointer relative indirect indexed y addressing modes. program counter (pc) program counter (pc) is a 16-bit counter that indicates the low-order 16 bits of the next program memory address to be executed. there is a bus interface unit between the program memory and the cpu, so that the program memory is accessed through the bus interface unit. this is described later. program bank register (pg) program bank register (pg) is an 8-bit register that indicates the high- order 8 bits of the next program memory address to be executed. when a carry occurs by incrementing the contents of the program counter, the contents of the program bank register (pg) is incremented by 1. also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the program counter (pc) by using a branch instruction, the contents of the program bank register (pg) is incremented or decremented by 1 so that programs can be written without worrying about bank boundaries. data bank register (dt) data bank register (dt) is an 8-bit register. with some addressing modes, a part of the data bank register (dt) is used to specify a memory address. the contents of data bank register (dt) is used as the high-order 8 bits of a 24-bit address. addressing modes that use the data bank register (dt) to specify the address are direct indirect, direct indexed x indirect, direct indirect indexed y, absolute, absolute bit, absolute indexed x, absolute indexed y, absolute bit relative, and stack pointer relative indirect indexed y. direct page register (dpr) direct page register (dpr) is a 16-bit register. its contents is used as the base address of a 256-byte direct page area. the direct page area is allocated in bank 0 16 , but when the contents of dpr is ff01 16 or more, the direct page area spans across bank 0 16 and bank 1 16 . all direct addressing modes use the contents of the direct page register (dpr) to generate the data address. when the low-order 8 bits contents of the direct page register (dpr) is 00 16 , the number of cycles required to generate an address is minimized. hence the low- order 8 bits contents of the direct page register (dpr) is usually set to 00 16 . processor status register (ps) processor status register (ps) is an 11-bit register. it consists of flags which indicate the result of operation and the processor interrupt priority level (ipl). branch operations can be performed by testing flags c, z , v, and n. the details of each processor status register bit are described below. 1. carry flag (c) the carry flag contains the carry or borrow generated by the alu after an arithmetic operation. this flag is also affected by shift or rotate instruction. this flag can be set or reset directly with the sec, clc instructions or with the sep, clp instructions. 2. zero flag (z) this zero flag is set when the result of an arithmetic operation or data transfer is zero and reset when it is not. this flag can be set or reset directly with the sep or clp instruction. 3. interrupt disable flag ( i ) when the interrupt disable flag is 1, all interrupts except watchdog ____ timer, dbc , and software interrupt are disabled. this flag is automatically set to 1 when an interrupt is accepted. it can be set or reset directly with the sei, cli instructions or sep and clp instructions. 4. decimal mode flag (d) the decimal mode flag determines whether addition and subtraction are performed in the binary or the decimal system. binary arithmetic is performed when this flag is 0. if it is 1, decimal arithmetic is performed with each word treated as the 2- or 4-digit number. arithmetic operation is performed with 4-digit number when the data length flag (m) is 0 and with 2-digit number when it is 1. decimal correction is automatically performed. (decimal operation is possible only with the adc and sbc instructions.) this flag can be set or reset with the sep or clp instruction. 5. index register length flag (x) the index register length flag determines whether index register x and index register y are used as 16-bit registers or as 8-bit registers. the registers are used as 16-bit registers when flag x is 0 and as 8- bit registers when it is 1. this flag can be set or reset with the sep or clp instruction. 6. data length flag (m) the data length flag determines whether the data has a length of 16 bits or that of 8 bits. the 16-bit length is selected when flag m is 0 and the 8-bit length is selected when it is 1. this flag can be set or reset with the sem, clm instructions or with the sep, clp instructions.
9 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 7. overflow flag (v) the overflow flag is effective only when addition or subtrac tion is performed with treating a word as a signed binary number. wh en the data length flag (m) is 0, the overflow flag is set if the result of addition or subtraction is outside the range between e 32768 and +32767. when the data length flag (m) is 1, the overflow f lag is set if the result of addition or subtraction is outside the rang e between e128 and +127. it is reset in the other cases. the overflow flag can also be set or reset directly with the sep or clv, clp instr uctions. 8. negative flag (n) the negative flag is set when the result of arithmetic opera tion or data transfer is negative (if data length flag (m) is 0, d ata bit 15 is 1. if data length flag (m) is 1, data bit 7 is 1.) it is reset in the other cases. it can also be set or reset with the sep or clp instructions. 9. processor interrupt priority level (ipl) the processor interrupt priority level (ipl) consists of 3 b its and determines the processor interrupt priority level (0 to 7). interrupt is enabled when the interrupt priority level of the device requ esting interrupt (the priority can be set using the interrupt contr ol register) is higher than the processor interrupt priority level. when int errupt is enabled, the current processor interrupt priority level is s aved in a stack and the processor interrupt priority level is replaced by the interrupt priority level of the device requesting the interr upt. refer to the section on interrupts for more details. bus interface unit the cpu operates on an internal clock ?s frequency. internal clock ?s frequency is twice the bus cycle frequency. in order to s peed up processing, a bus interface unit is used to pre-fetch instru ctions when the data bus is idle. the bus interface unit synchronizes th e cpu and the bus and pre-fetches instructions. figure 4 shows the relationship between the cpu and the bus interface unit. the bus interface unit has a program address register, a 3-byte inst ruction queue buffer, a data address register, and a 2-byte data buf fer. the bus interface unit obtains an instruction code from the memory and stores it in the instruction queue buffer, obtains data from the memory and stores it in the data buffer, or writes the data from the data buffer to the memory. fig. 4 relationship between the cpu and the bus interface u nit cpu bus interface unit e ale byte hold bhe r/ w d 15 e d 8 a 23 e a 0 d 7 e d 0 d' 15 e d' 8 control signal d' 7 e d' 0 a' 23 e a' 0
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 10 port p2 e ale port p2 e ale internal clock internal clock port p2 e ale ad ad ad a + 1 d a d a + 1 d ad a + 1 d (1) (2) (3) (4) (5) (6) access time access time access time access time access time access time a dd a + 1 a d a d a + 1 d (7) (8) (9) (10) access time access time d a a + 1 d ad a + 1 d access time access time a : address d : data port p2 e ale port p2 e ale port p2 e ale port p2 e ale port p2 e ale port p2 e ale port p2 e ale the bus interface unit operates using one of the waveforms (1) to (10) shown in figure 5. the standard waveforms are (1) and (2). the ale signal is used to latch only the address signal from the multiplexed signal containing data and address. _ s ignal e becomes l when the bus interface unit reads an instruction code or data from the memory or when it writes data to the memory. _ whether to perform read or write is controlled by signal r/ w . when _ signal r/ w is h, read is performed; when l, write is performed. __ in the external bus mode b, signals e and r/ w are not directly output to the outside of the chip. in the memory expansion mode or the ___ ___ ____ microprocessor mode, read signal rde and write signals wel , weh _ ___ are output to the outside of the chip. while signal e is l, signal rde _ ___ ___ becomes l at reading. while signal e is l, signals wel and weh become l at writing. waveform (1) in figure 5 is used to access a single byte or two bytes simultaneously. to read or write two bytes simultaneously, the first address accessed must be even. furthermore, when accessing an external memory area in the memory expansion mode or the microprocessor mode, set the bus width selection input pin (byte) to l (external data bus has a width of 16 bits). the data bus in the internal memory area is always treated as the 16-bit bus independent of byte. fig. 5 bus access timing _ ___ while signal e is l in the external bus mode b, signal rde ___ ____ becomes l (in the read cycle) or signals wel and weh become l (in the write cycle).
11 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer the cpu notifies the bus interface unit when performing data read or write. at this time, the bus interface unit halts the cpu if the bus interface unit is already using the bus or if there is a request with higher priority. when data read or write is enabled, the bus interface unit uses one of the waveforms from (1) to (10) in figure 5 to perform the operation. during data read, the cpu waits until the entire data is stored in the data buffer. the bus interface unit sends the address received from the cpu to the address bus. then it reads the memory when signal _ e is l and stores the result in the data buffer. during data write, the cpu writes the data in the data buffer and the bus interface unit writes it to the memory . therefore, the cpu can proceed to the next step without waiting for write completed. the bus interface unit sends the address received from the cpu to the address _ bus. then when signal e is l, the bus interface unit sends the data in the data buffer to the data bus and writes it to the memory. when performing 16-bit data read or write, waveform (2) is used to access each byte one by one if the conditions for simultaneously accessing two bytes are not satisfied. however, when prefetching the instruction code, if the address of the instruction code is odd, waveform (1) is used, and only one byte is read in the instruction queue buffer. ___ access to the even/odd address is controlled by signals bhe and a 0 . ___ in the external bus mode b, signal bhe is not directly output to the ___ ___ outside of the chip. write signals ( wel , weh ) are generated corresponding to the accessed address (even or odd). bit 2 of processor mode register 0 (address 5e 16 ) is the wait bit. when the external memory area is accessed in the memory expansion mode or the microprocessor mode with this bit set to 0, the width of _ signal e is extended and access time can be extended. there are two ways to extend the access time and they are selected with bit 0 of the processor mode register 1 (address 5f 16 ). _ when this bit is set to 1, the l width of signal e in (1) becomes twice as long as in (3) and the access time becomes 1.5 times (wait _ 1). when this bit is set to 0, signals ale and e in (1) are extended as in (7) and the access time is doubled (wait 0). however, these signals are not extended when accessing the internal memory area. when the wait bit is set to 1, these signals are not extended when accessing any memory area regardless of the bit 0 of the processor mode register 1. waveforms (4), (5), and (6) show the entire waveform, first half, and last half respectively of waveform (2) for wait 1. waveforms (8), (9), and (10) show the entire waveform, first half, and last half respectively of waveform (2) for wait 0. instruction code read, data read, and data write are described below. instruction code read will be described first. the cpu obtains instruction codes from the instruction queue buffer and executes them. the cpu notifies the bus interface unit that it is requesting an instruction code during an instruction code request cycle. if the requested instruction code is not yet stored in the instruction queue buffer, the bus interface unit halts the cpu until more instructions than requested is stored in the instruction queue buffer. even if there is no instruction code request from the cpu, the bus interface unit reads instruction codes from the memory and stores them in the instruction queue buffer when the instruction queue buffer is empty or when only one instruction code is stored and the bus is idle on the next cycle. this is referred to as instruction pre-fetching. normally , when reading an instruction code from the memory, if the accessed address is even, the next odd address is read together with the instruction code and stored in the instruction queue buffer. however, in the memory expansion mode or the microprocessor mode, only one byte is read and stored in the instruction queue buffer if the following conditions are satisfied. ? the address to be read is in the external memory area when the external data bus has an 8-bit width (byte = h). ? the address to be read is odd. therefore, waveform (1), (3) or (7) in figure 5 is used for instruction code read. data read and write are described below.
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 12 interrupts table 1 shows the interrupt sources and the corresponding interrupt vector addresses. reset is also treated as a source of interrupt and is described in this section. ___ dbc is an interrupt used only for debugging. ___ interrupts other than reset, dbc , watchdog timer, zero divide, and brk instruction all have their respective interrupt control registers. table 2 shows the addresses of the interrupt control registers and figure 6 shows the bit configuration of the interrupt control register. the interrupt request bit is automatically cleared by hardware during reset or when processing an interrupt. also, interrupt request bits ___ other than dbc and watchdog timer can be cleared by software. ___ ___ int 0 to int 2 are external interrupts, and whether to cause an interrupt at the input level (level sense) or at the edge (edge sense) can be selected with the level sense/edge sense selection bit. furthermore, the polarity of the interrupt input can be selected with a polarity selection bit. ___ in the int 2 /key input interrupt, whether to input an interrupt request ___ __ __ from the int 2 pin or the ki 0 C ki 3 pins can be selected by bit 7 of the port function control register (refer to figure 11). timer and uart interrupts are described in the respective section. the priority of interrupts when multiple interrupts are caused simultaneously is partially fixed by hardware, but it can also be adjusted by software as shown in figure 7. the hardware priority is fixed as follows: ___ reset > dbc > watchdog timer > other interrupts table 1. interrupt sources and the interrupt vector addresses fig. 6 interrupt control register bit configuration 7 interrupt priority level selection bits 6543 2 1 0 interrupt request bit 0 : no interrupt 1 : interrupt interrupt control register configuration for timers a0 to a4, timers b0 to b2, uart0, uart1 and a-d/uart2 trans./rece. 7 interrupt priority level selection bits 6543 2 1 0 interrupt request bit 0 : no interrupt 1 : interrupt polarity selection bit 0 : interrupt request bit is set at h level for level sense or at the falling edge for edge sence. 1 : interrupt request bit is set at l level for level sense or at the rising edge for edge sense. level sense/edge sense selection bit 0 : edge sense 1 : level sense interrupt control register configuration for int 0 to int 2 /key input interrupts vector addresses a-d/uart2 trans./rece. 00ffd6 16 00ffd7 16 uart1 transmit 00ffd8 16 00ffd9 16 uart1 receive 00ffda 16 00ffdb 16 uart0 transmit 00ffdc 16 00ffdd 16 uart0 receive 00ffde 16 00ffdf 16 timer b2 00ffe0 16 00ffe1 16 timer b1 00ffe2 16 00ffe3 16 timer b0 00ffe4 16 00ffe5 16 timer a4 00ffe6 16 00ffe7 16 timer a3 00ffe8 16 00ffe9 16 timer a2 00ffea 16 00ffeb 16 timer a1 00ffec 16 00ffed 16 timer a0 00ffee 16 00ffef 16 ___ int 2 /key input 00fff0 16 00fff1 16 ___ int 1 00fff2 16 00fff3 16 ___ int 0 00fff4 16 00fff5 16 watchdog timer 00fff6 16 00fff7 16 ___ dbc (unusable) 00fff8 16 00fff9 16 brk instruction 00fffa 16 00fffb 16 zero divide 00fffc 16 00fffd 16 reset 00fffe 16 00ffff 16
13 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer interrupt control registers addresses a-d/uart2 trans./rece. interrput control register 000070 16 uart0 transmit interrput control register 000071 16 uart0 receive interrput control register 000072 16 uart1 transmit interrput control register 000073 16 uart1 receive interrupt control register 000074 16 timer a0 interrupt control register 000075 16 timer a1 interrupt control register 000076 16 timer a2 interrupt control register 000077 16 timer a3 interrupt control register 000078 16 timer a4 interrupt control register 000079 16 timer b0 interrupt control register 00007a 16 timer b1 interrupt control register 00007b 16 timer b2 interrupt control register 00007c 16 ___ int 0 interrupt control register 00007d 16 ___ int 1 interrupt control register 00007e 16 ___ int 2 /key input interrupt control register 00007f 16 table 2. addresses of interrupt control registers interrupts caused by a brk instruction and when dividing by zero are software interrupts and are not included in this list. other interrupts previously mentioned are a-d converter, uart, timer, int interrupts. the priority of these interrupts can be changed by changing the interrupt priority level selection bits of the corresponding interrupt control register with software. figure 8 shows a diagram of the interrupt priority detection circuit. when an interrupt is caused, the each interrupt device compares its own priority with the priority from above and if its own priority is higher, then it sends the priority below and requests the interrupt. if the priorities are the same, the one above has priority. this comparison is repeated to select the interrupt with the highest priority among the interrupts that are being requested. finally the selected interrupt is compared with the processor interrupt priority level (ipl) contained in the processor status register (ps), and the request is accepted if it is higher than ipl and the interrupt disable flag (i) is 0. the request is not accepted if flag i is 1. the reset, ___ dbc , and watchdog timer interrupts are not affected by the interrupt disable flag (i). when an interrupt is accepted, the contents of the processor status register (ps) is saved to the stack and the interrupt disable flag (i) is set to 1. furthermore, the interrupt request bit of the accepted interrupt is cleared to 0 and the processor interrupt priority level (ipl) in the processor status register (ps) is replaced by the priority level of the accepted interrupt. therefore, multiple interrupts are possible by resetting the interrupt disable flag (i) to 0 and enable further interrupts. ___ for reset, dbc , watchdog timer, zero divide, and brk instruction interrupts, which do not have an interrupt control register, the processor interrupt level (ipl) is set as shown in table 3. priority detection is performed by latching the interrupt request bit and interrupt priority level selection bits so that they do not change. they are sampled at the first half and latched at the last half of the operation code fetch cycle. because priority detection takes some time, no sampling pulse is generated for a certain interval even if it is the next operation code fetch cycle. fig. 8 interrupt priority detection circuit fig. 7 interrupt priority priority is determined by hardware a ? watchdog timer dbc reset a-d converter, uart, timer, int interrupts priority can be changed by software inside 1 2 3 4 4 timer watchdog a-d/uart2 trans./rece. level 0 int 0 uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 1 ipl interrupt disable flag(i) dbc reset interrupt request
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 14 interrupt priority detection time selection bits bit 5 bit 4 0 0 7 cycles of 0 1 4 cycles of 1 0 2 cycles of fig. 10 processor mode register 0 configuration fig. 9 interrupt priority detection time as shown in figure 9, there are three different interrupt priority detection time from which one is selected by software. after the selected time has elapsed, the interrupt which has the highest priority is determined and is processed after the current instruction execution has been completed. the time is selected with bits 4 and 5 of the processor mode register 0 (address 5e 16 ) shown in figure 10. table 4 shows the relationship between these bits and the number of cycles. after a reset, the processor mode register 0 is initialized to 00 16 . therefore, the longest time is selected. however, the shortest time should be selected by software. table 3. value set in processor interrupt level (ipl) during an interrupt table 4. relationship between interrupt priority detection time selec- tion bits and number of cycles : internal clock number of cycles 7 processor mode register 0 (5e 16 ) 6 5 4 3 2 1 0 address processor mode bits 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode wait bit 0 : wait 1 : no wait software reset bit the processor is reset when this bit is set to 1 . interrupt priority detection time selection bits 0 0 : select 0 in figure 9 0 1 : select 1 in figure 9 1 0 : select 2 in figure 9 always 0 clock 1 output selection bit 0 : no 1 output 1 : 1 output 0 0 1 2 internal clock operation code fetch cycle sampling pulse priority detection time select one from 0 to 2 with bits 4 and 5 of the processor mode register 0 interrupt types setting value reset 0 ___ dbc 7 watchdog timer 7 zero divide not change value of ipl. brk instruction not change value of ipl.
15 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer __ __ pull-up resistors (transistors) can be added to the ki 0 to ki 3 pins by setting 1 to the port p10 pull-up selection bit and 0 to the contents of the port p10 i (i = 4 to 7) direction register. similarly, a pull-up resistor ___ can be added to the int 2 pin by setting 1 to the port p6 pull-up selection bit 1 and 0 to the content of the port p6 4 direction register. with the key input interrupt and the pull-up function, the key input circuit is easily composed. ___ fig. 12 int 2 /key input interrupt input circuit block diagram ___ by setting the port function control register, the int 2 /key input interrupt function can be switched to the key input interrupt function which __ __ uses the ki 0 to ki 3 inputs. figure 11 shows the bit configuration of the ___ port function control register, and figure 12 shows the int 2 /key input interrupt input circuit block diagram. when the key input interrupt selection bit of the port function control ___ ___ register is 0, a signal is input from the int 2 pin to the int 2 /key input ___ interrupt control circuit and the int 2 interrupt is normally performed. when the key input interrupt selection bit is 1, signals input from __ __ the ki 0 to ki 3 pins are inverted, and then the logical sum of these ___ signals is input to the int 2 interrupt control circuit. in this case, the __ __ external interrupt which uses the ki 0 to ki 3 pins is performed. (pins __ __ ki 0 to ki 3 correspond to ports p10 4 to p10 7 , respectively.) additionally, ___ by setting the port p6 pull-up selection bit 1 to 1, the int 2 input is added to that logical sum, so that the external interrupt which uses __ __ ___ the inputs ki 0 to ki 3 and int 2 is performed. when using the key input interrupt, it is necessary to select the edge sense which uses the ___ falling edge by setting the int 2 /key input interrupt control register. because of this selection, a key input interrupt request occurs when __ __ ___ l is input to one of the ki 0 to ki 3 and int 2 pins. the interrupt vector ___ and the interrupt control register are common to the int 2 and key input interrupts. int 2 /key input interrupt control register interrupt control register p6 4 / int 2 p10 7 / ki 3 p10 5 / ki 1 p10 6 / ki 2 p10 4 / ki 0 int 2 /key input interrupt request key input interrupt selection bit (address 7f 16 ) when the key input interrupt is selected, it is necessary to select the edge sense which uses falling edge. pull?p transistor port p10 pull-up selection bit port p10 7 direction register 0 1 pull?p transistor pull?p transistor pull?p transistor port p6 pull-up selection bit 1 port p6 4 direction register 1 0 port p6 pull-up selection bit 1 pull?p transistor
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 16 fig. 11 bit configuration of port function control register standby state selection bit 0: pins p0 C p3 as external bus output 1: pins p0 C p3 as port output sub-clock output selection bit/timer b2 clock source selection bit ? port-xc selection bit = 0 (sub-clock not used) timer b2 (event counter mode) clock source selection 0: tb2 in input 1: main clock divided by 32 ? port-xc selection bit = 1 (sub-clock used) sub-clock output selection 0: function as port p6 7 pin 1: output sub-clock sub from p6 7 /tb2 in / sub pin timer b1 internal connect selection bit 0: no internal connect 1: internal connect to timer b2 port p6 pull-up selection bit 0 0: with no pull-up transistor for pins p6 2 / int 0 , p6 3 / int 1 1: with pull-up transistor for pins p6 2 / int 0 , p6 3 / int 1 0: always 0 port p6 pull-up selection bit 1 ? key input interrupt selection bit = 0 0: with no pull-up transistor for p6 4 / int 2 pin 1: with pull-up transistor for p6 4 / int 2 pin ? key input interrupt selection bit = 1 0: with port function, no pull-up transistor for p6 4 / int 2 pin 1: with key input interrupt, pull-up transistor for p6 4 / int 2 pin port p10 pull-up selection bit 0: with no pull-up transistor for pins p10 4 C p10 7 1: with pull-up transistor for pins p10 4 C p10 7 key input interrupt selection bit 0: int 2 interrupt 1: key input interrupt 7654 0 321 port function control register address 6d 16 0
17 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer data bus (odd) data bus (even) count start flag down count up-down flag (high-order 8 bits) counter(16) up/down polarity selection timer (gate function) tai in f 2 f 16 f 64 f 512 clock source selection (i = 0 ?4) ?timer ?one-shot ?pulse width modulation event counter external trigger always decremented except in event count mode timer a0 47 16 46 16 timer a1 49 16 48 16 timer a2 4b 16 4a 16 timer a3 4d 16 4c 16 timer a4 4f 16 4e 16 address (low-order 8 bits) (address 40 16 ) pulse output tai out (i = 0 ?4) (address 44 16 ) reload register(16) toggle flip-flop timer there are eight 16-bit timers. they are divided by type into timer a(5) and timer b(3). the timer i/o pins are also used as i/o pins for ports p5 and p6. to use these pins as timer input pins, the port direction register bit corresponding to the pin must be cleared to 0 to specify the input mode. timer a figure 13 shows a block diagram of timer a. timer a has four modes; timer mode, event counter mode, one-shot pulse mode, and pulse width modulation mode. the mode is selected with bits 0 and 1 of the timer ai mode register (i = 0 to 4). each of these modes is described below. (1) timer mode [00] figure 14 shows the bit configuration of the timer ai mode register during timer mode. bits 0, 1, and 5 of timer ai mode register must always be 0 in the timer mode. bit 3 is ignored if bit 4 is 0. bits 6 and 7 are used to select the timer counter source. the counting of the selected clock starts when the count start flag is 1 and stops when it is 0. figure 15 shows the bit configuration of the count start flag. the counter is decremented. an interrupt is caused and the interrupt request bit of the timer ai interrupt control register is set when the contents becomes 0000 16 . at the same time, the contents of the reload register are transferred to the counter, and count is continued. fig. 13 block diagram of timer a
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 18 when bit 2 of the timer ai mode register is 1, the output is generated from tai out pin. the output is toggled each time the contents of the counter reaches to 0000 16 . when the contents of the count start flag is 0, l is output from tai out pin. when bit 2 is 0, tai out can be used as a normal port pin. when bit 4 is 0, tai in can be used as a normal port pin. when bit 4 is 1, counting is performed only while the input signal from the tai in pin is h or l as shown in figure 16. therefore, this can be used to measure the pulse width of the tai in input signal. whether to count while the input signal is h or while it is l is determined by bit 3. when bit 3 is 1, counting is performed while the tai in pin input signal is h and when bit 3 is 0, counting is performed while it is l. note that the duration of h or l on the tai in pin must be two or more cycles of the timer count sourse. when data is written to the timer ai register with timer ai halted, the same data is also written to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the counter is reloaded with new data from the reload register at the next reload time. the contents of the counter can be read at any time. when the value set in the timer ai register is n, the timer frequency dividing ratio is 1/(n + 1). fig. 14 timer ai mode register bit configuration during timer mode 70 0 0 : always ?0?in timer mode 0 0 : no pulse output (tai out is normal port pin) 1 : pulse output 0 5 : no gate function (tai in is normal port pin) 1 0 : count only while tai in input is ? 1 1 : count only while tai in input is ? 62 3 4 51 00 0 : always ??in timer mode clock source selection bit 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 timer a0 mode register 56 16 timer a1 mode register 57 16 timer a2 mode register 58 16 timer a3 mode register 59 16 timer a4 mode register 5a 16 addresses
19 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer fig. 15 count start flag bit configuration fig. 16 count waveform when gate function is available 70 654321 count start flag (stop at ?? start at ?? timer a0 count start flag timer b2 count start flag timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag timer b0 count start flag timer b1 count start flag address 40 16 selected clock source f i tai n timer mode register bit 4 bit 3 10 11 bit 4 bit 3 timer mode register 11
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 20 (2) event counter mode [01] figure 17 shows the bit configuration of the timer ai mode register during the event counter mode. in the event counter mode, the bit 0 of the timer ai mode register must be 1 and bits 1 and 5 must be 0. the input signal from the tai in pin is counted when the count start flag shown in figure 15 is 1 and counting is stopped when it is 0. count is performed at the fall of the input signal when bit 3 is 0 and at the rise of the signal when it is 1. in the event counter mode, whether to increment or decrement the count can be selected with the up-down flag or the input signal from the tai out pin. when bit 4 of the timer ai mode register is 0, the up-down flag is used to determine whether to increment or decrement the count (decrement when the flag is 0 and increment when it is 1). figure 18 shows the bit configuration of the up-down flag. when bit 4 of the timer ai mode register is 1, the input signal from the tai out pin is used to determine whether to increment or decrement the count. however, note that bit 2 must be 0 if bit 4 is 1. because tai out pin becomes an output pin with pulse output if bit 2 is 1. the count is decremented when the input signal from the tai out pin is l and incremented when it is h. determine the level of the input signal from the tai out pin before an effective edge is input to the tai in pin. an interrupt request signal is generated and the interrupt request bit of the timer ai interrupt control register is set when the counter reaches 0000 16 (decrement count) or ffff 16 (increment count). at the same time, timers a0 and a1 transfer the contents of the reload register to the counter and continue counting. timers a2, a3, and a4 transfer the contents of the reload register to the counter and continue count when bit 6 of the corresponding timer ai mode register is 0, but when bit 6 is 1, they continue counting without transferring the contents of the reload register to the counter. when bit 2 is 1, the waveform of which polarity is reversed each time the counter reaches 0000 16 (decrement count) or ffff 16 (increment count) is output from tai out pin. if bit 2 is 0, the tai out pin can be used as a normal port pin. however, if bit 4 is 1 and the tai out pin is used as an output pin, the output from the tai out pin changes the count direction. therefore, bit 4 must be 0 unless the output from the tai out pin is used to select the count direction. data write and data read are performed in the same way as for the timer mode. that is, when data is written to timer ai which is halted, it is also written to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not the counter. the counter is reloaded with new data from the reload register at the next reload time and continues counting. for timers a2, a3, and a4, the contents of the reload register is not reloaded in the counter when bit 6 of the corresponding timer ai mode register is 1. the contents of the counter can be read at any time. fig. 18 up-down flag bit configuration fig. 17 timer ai mode register bit configuration during event counter mode timer a0 up-down flag 7 6543 2 1 0 44 16 addresses up-down flag timer a1 up-down flag timer a2 up-down flag timer a4 up-down flag timer a3 two-phase pulse signal processing selection bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a2 two-phase pulse signal processing selection bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a4 two-phase pulse signal processing selection bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a3 up-down flag this bit is available for timer a3. 0 : two-phase pulse signal processing in the same manner as timer a2 1 : two-phase pulse signal processing in the same manner as timer a4 0 1 : always ?1?in event counter mode 7 6543 2 1 0 001 0 : no pulse output 1 : pulse output 0 : count at the falling edge of input signal 1 : count at the rising edge of input signal 0 : increment or decrement according to up-down flag 1 : increment or decrement according to tai out pin input signal level 0 : always ??in event counter mode this bit is available for times a2, a3, and a4. 0 : reload 1 : no reload timer a0 mode register 56 16 timer a1 mode register 57 16 timer a2 mode register 58 16 timer a3 mode register 59 16 timer a4 mode register 5a 16 addresses
21 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer fig. 21 timer aj mode register bit configuration when performing two-phase pulse signal processing in event counter mode fig. 20 two-phase pulse signal processing operation of timer a4 fig. 19 two-phase pulse signal processing operation of timer a2 furthermore, in the event counter mode, whether to increment or decrement the counter can also be determined by supplying two kinds of pulses of which phases differ by 90 to timer a2, a3, or a4. there are two types of two-phase pulse signal processing operations. one uses timer a2 and the other uses timer a4. timer a3 can select one of these two operations with bit 7 of the timer a3 mode register. in both processing operations, two kinds of pulses of which phases differ by 90 are input to the taj out (j = 2 to 4) pin and taj in pin respectively. after the level of the ta2 out pin changes from l to h with timer a2 used, as shown in figure 19, the count is incremented when a rising edge is input to the ta2 in pin and the count is decremented when the falling edge is input. for timer a4, as shown in figure 20, when a phase related pulse with a rising edge input to the ta4 in pin is input after the level of ta4 out pin changes from l to h, the count is incremented at the respective rising edge and falling edge of the ta4 out pin and ta4 in pin. when a phase related pulse with a falling edge input to the ta4 out pin is input after the level of ta4 in pin changes from h to l, the count is decremented at the respective rising edge and falling edge of the ta4 in pin and ta4 out pin. when performing this two-phase pulse signal processing, bits 0 and 4 of the timer aj mode register must be set to 1 and bits 1, 2, 3, and 5 must be set to 0 as shown in figure 21. bit 7 is used to select whether to perform two-phase pulse signal processing for timer a3 in the same manner as timer a2 or as timer a4. when this bit is 0, two-phase pulse signal processing for timer a3 is performed in the same manner as timer a2 and when it is 1, it is performed in the same manner as timer a4. this bit is ignored for timers a2 and a4. note that bits 5, 6, and 7 of the up-down flag (address 44 16 ) are the two-phase pulse signal processing selection bits for timers a2, a3, and a4, respectively. each timer operates in the normal event counter mode when the corresponding bit is 0 and performs two-phase pulse signal processing when it is 1. count is started by setting the count start flag to 1. data write and read are performed in the same way as for the normal event counter mode. note that the port direction register of the input port must be set to the input mode because two-phase pulse signal is input. also, there can be no pulse output in this mode. ta2 out ta2 in increment count increment count increment count decrement count decrement count decrement count ta4 out ta4 in increment count at each edge decrement count at each edge increment count at each edge decrement count at each edge addresses 0 1 : always ?1?in event counter mode 7 6543 2 1 0 001 0 1 0 0 : always ?100?when processing two-phase pulse signal timer a2 mode register 58 16 timer a3 mode register 59 16 timer a4 mode register 5a 16 100 0 : reload 1 : no reload this bit is avilable for timer a3 0 : two-phase pulse signal processing in the same manner as timer a2 1 : two-phase pulse signal processing in the same manner as timer a4
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 22 (3) one-shot pulse mode [10] figure 22 shows the bit configuration of the timer ai mode resister during the one-shot pulse mode. in the one-shot pulse mode, bit 0 and bit 5 must be 0 and bit 1 and bit 2 must be 1. the trigger is enabled when the count start flag is 1. the trigger can be generated by software, or it can be input from the tai in pin. software trigger is selected when bit 4 is 0, and the input signal from the tai in pin is used as the trigger when bit 4 is 1. bit 3 is used to determine whether to trigger at the fall of the trigger signal or at the rise. the trigger is at the fall of the trigger signal when bit 3 is 0 and at the rise of the trigger signal when bit 3 is 1. software trigger is generated by setting the bit of the one-shot start flag corresponding to each timer. figure 23 shows the bit configuration of the one-shot start flag. as shown in figure 24, when a trigger signal is received, the counter counts the clock selected by bits 6 and 7. if the contents of the counter is not 0000 16 , the tai out pin goes h when a trigger signal is received. the count direction is decrement. when the counter reaches 0001 16 , the tai out pin goes l and count is stopped. the contents of the reload register is transferred to the counter. at the same time, an interrupt request signal is generated, and the interrupt request bit of the timer ai interrupt control register is set. this is repeated each time a trigger signal is received. the output pulse width is 1 pulse frequency of the selected clock 5 (counters value at the time of trigger). if the count start flag is 0, the level of the tai out pin goes l. therefore, the counters value corresponding to the desired pulse width must be written to timer ai before setting 1 to the timer ai count start flag. as shown in figure 25, a trigger signal can be received before the operation for the previous trigger signal is completed. in this case, the contents of the reload register is transferred to the counter by the trigger, and then that value is decremented. except when retriggering while operating, the contents of the reload register is not transferred to the counter by triggering. when retriggering, there must be at least two timer count source cycles before a new trigger can be issued. fig. 22 timer ai mode register bit configuration during one-shot pulse mode timer a0 mode register 56 16 timer a1 mode register 57 16 timer a2 mode register 58 16 timer a3 mode register 59 16 timer a4 mode register 5a 16 addresses 1 : always ??in one-shot pulse mode 0 5 : software trigger 1 0 : trigger at the falling edge of tai in input 1 1 : trigger at the rising edge of tai in input 0 : always ??in one-shot pulse mode clock source selection 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 1 0 : always ?0?in one-shot pulse mode 7 6543 2 1 0 010 1
23 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer data write is performed in the same way as for the timer mode. when data is written in timer ai halted, it is also written to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the counter is reloaded with new data from the reload register at the next reload time and continues counting. undefined data is read when timer ai is read. fig. 23 one-shot start flag bit configuration fig. 25 example when trigger is re-issued during pulse output fig. 24 pulse output example when external rising edge is selected 70 654321 one-shot start flag timer a0 one-shot start flag timer a4 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag address 42 16 selected clock source f i tai in (rising edge is selected) tai out selected clock source f i tai in (rising edge is selected) tai out 70 654321 one-shot start flag timer a0 one-shot start flag timer a4 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag address 42 16 selected clock source f i tai in (rising edge is selected) tai out selected clock source f i tai in (rising edge is selected) tai out in this case, the contents of the reload register is in this case, the contents of the reload register is 0004 16 . 0003 16 .
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 24 (4) pulse width modulation mode [11] figure 26 shows the bit configuration of the timer ai mode register during the pulse width modulation mode. in the pulse width modulation mode, bits 0, 1, and 2 must be set to 1. bit 5 is used to determine whether to perform as the 16-bit length pulse width modulator or the 8-bit length pulse width modulator. 16- bit length pulse width modulator is selected when bit 5 is 0 and 8-bit length pulse width modulator is selected when bit 5 is 1. the 16-bit length pulse width modulator is described first. the pulse width modulator can be started with a software trigger or with an input signal from a tai in pin (external trigger). the software trigger mode is selected when bit 4 is 0. pulse width modulator is started and pulse is output from the tai out pin when the timer ai start flag is set to 1. the external trigger mode is selected when bit 4 is 1. pulse width modulator starts when a trigger signal is input from the tai in pin when the timer ai start flag is 1. whether to trigger at the fall or rise of the trigger signal is determined by bit 3. the trigger is at the fall of the trigger signal when bit 3 is 0 and at the rise when it is 1. when data is written to timer ai with the pulse width modulator halted, it is written to the reload register and the counter. then when the timer ai start flag is set to 1 and a software trigger or an external trigger is issued to start modulation, the waveform shown in figure 27 is output continuously. once modulation is started, triggers are not accepted. when the value in the reload register is m, the duration h of pulse is the reload register and the counter are both divided into 8-bit halves. the low-order 8 bits function as a prescaler and the high-order 8 bits function as the 8-bit length pulse width modulator. the prescaler counts the clock selected by bits 6 and 7. a pulse is generated when the counter reaches 0000 16 as shown in figure 28. at the same time, the contents of the reload register is transferred to the counter, and count is continued. fig. 26 timer ai mode register bit configuration during pulse width modulation mode an interrupt request signal is generated and the interrupt request bit of the timer ai interrupt control register is set at each fall of the output pulse. the width of the output pulse is changed by updating timer data. the update can be performed at any time. the output pulse width is changed at the rise of the pulse after data is written to the timer. the contents of the reload register is transferred to the counter just before the rise of the next output pulse so that the pulse width is changed from the next output pulse. undefined data is read when timer ai is read. the 8-bit length pulse width modulator is described next. the 8-bit length pulse width modulator is selected when bit 5 of the timer ai mode register is 1. 1 selected clock frequency 5 m and the output pulse period is 1 selected clock frequency 5 (2 16 C 1). 76 54 321 0 11 1 timer a0 mode register 56 16 timer a1 mode register 57 16 timer a2 mode register 58 16 timer a3 mode register 59 16 timer a4 mode register 5a 16 addresses 1 : always ??in pulse width modulation mode 0 5 : software trigger 1 0 : trigger at the falling of tai i n input 1 1 : trigger at the rising of tai in input clock source selection bit 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 1 1 : always ?1?in pulse width modulation mode 0 : 16 bit pulse width modulator 1 : 8 bit pulse width modulator
25 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 1 selected clock frequency 5 (n + 1). the high-order 8 bits function as an 8-bit length pulse width modulator using this pulse as input. its operation is the same as for 16-bit length pulse width modulator except it has a length of 8 bits. when the high- order 8 bits contents of the reload register is m, the duration h of pulse is therefore, if the low-order 8 bits of the reload register is n, the period of the generated pulse is 1 selected clock frequency 5 (n + 1) 5 m. 1 selected clock frequency 5 (n + 1) 5 (2 8 C 1). fig. 28 8-bit length pulse width modulator output pulse example fig. 27 16-bit length pulse width modulator output pulse example and the output pulse period is selected clock source f i tai in (rising edge is selected) tai out 1 / f i 5 (2 16 ?1) 1 / f i 5 (m) this trigger is not accepted in this case, the contents of the reload register is 0003 16. selected clock source f i 8-bit length pulse width modulator output (when m = 2) tai in (falling edge is selected) 1 / f i 5 (n + 1) 1 / f i 5 (n + 1) 5 (m) 1 / f i 5 (n + 1) 5 (2 8 ?1) (when n = 2) prescaler output
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 26 timer b figure 29 shows a block diagram of timer b. timer b has three modes; timer mode, event counter mode, and pulse period measurement/pulse width measurement mode. the mode is selected with bits 0 and 1 of the timer bi mode register (i = 0 to 2). timer b2 can also be used as the clock timer of which clock source is the main clock or the sub-clock divided by 32. additionally, timer b2 can be internally connected to timer b1 (cascade connection). each of these modes is described below. (1) timer mode [00] figure 30 shows the bit configuration of the timer bi mode register during the timer mode. bits 0 and 1 of the timer bi mode register must always be 0 in the timer mode. bits 6 and 7 are used to select the clock source. the counting of the selected clock starts when the count start flag is 1 and stops when it is 0. as shown in figure 15, the timer bi count start flag is at the same address as the timer ai count start flag. the count is decremented. when the contents of the counter becomes 0000 16 , an interrupt request occurs and the interrupt request bit of the timer bi interrupt control register is set. at the same time, the contents of the reload register is stored in the counter, and count is continued. timer bi does not have a pulse output function or a gate function like timer a. when data is written to timer bi halted, it is written to the reload register and the counter. when data is written to timer bi which is busy, the data is written to the reload register, but not to the counter. the counter is reloaded with new data from the reload register at the next reload time and continues counting. the contents of the counter can be read at any time. fig. 29 timer b block diagram f 2 f 16 f 64 f 512 ? timer ? pulse period measurement/pulse width measurement polarity selection and edge pulse generator event counter count start flag addresses timer b0 51 16 50 16 timer b1 53 16 52 16 timer b2 55 16 54 16 tbi in (i = 0 C 2) (address 40 16 ) counter reset circuit clock source selection data bus (odd) (low-order 8 bits) data bus (even) (high-order 8 bits) counter (16) reload register (16) f c32 (note 1) tb2 overflow signal (note 2) notes 1. clock source of clock timer; only timer b2 can select it (refer to fig. 65) 2. only timer b1 can select it (internal connect mode)
27 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer (2) event counter mode [01] figure 31 shows the bit configuration of the timer bi mode register during the event counter mode. in the event counter mode, the bit 0 of the timer bi mode register must be 1 and bit 1 must be 0. the input signal from the tbi in pin is counted when the count start flag is 1, and counting is stopped when it is 0. counting is performed at the fall of the input signal when bits 2 and 3 are 0 and at the rise of the input signal when bit 3 is 0 and bit 2 is 1. when bit 3 is 1 and bit 2 is 0, counting is performed at the rise and fall of the input signal. when the sub-clock (32 khz) oscillation circuit is used and others, and the event counter mode is selected, timer b2 functions as the clock timer and the original functions as timer b2 in the event counter mode are lost. for details, refer to (4) clock timer. when the internal connect mode which connects timer b1 to timer b2 is selected, the original function as timer b1 in the event counter mode is lost. for details, refer to (5) internal connect mode. data write, data read, and interrupt generation are performed in the same way as for the timer mode. (3) pulse period measurement/pulse width measurement mode [10] figure 32 shows the bit configuration of the timer bi mode register during the pulse period measurement/pulse width measurement mode. in the pulse period measurement/pulse width measurement mode, bit 0 must be 0 and bit 1 must be 1. bits 6 and 7 are used to select the clock source. the selected clock is counted when the count start flag is 1, and counting stops when it is 0. the pulse period measurement mode is selected when bit 3 is 0. in the pulse period measurement mode, the selected clock is counted during the interval starting at the fall of the input signal from the tbi in pin to the next fall or at the rise of the input signal to the next rise. and then, the result is stored in the reload register. in this case, the reload register acts as a buffer register. when bit 2 is 0, the clock is counted from the fall of the input signal to the next fall. when bit 2 is 1, the clock is counted from the rise of the input signal to the next rise. in the case of counting from the fall of the input signal to the next fall, counting is performed as follows. as shown in figure 33, when the fall of the input signal from tbi in pin is detected, the contents of the counter is transferred to the reload register. next the counter is cleared and count is started from the next clock. when the fall of the next input signal is detected, the contents of the counter is transferred to the reload register once more, the counter is cleared, and counting is started. the period from the fall of the input signal to the next fall is measured in this way. after the contents of the counter is transferred to the reload register, an interrupt request signal is generated and the interrupt request bit of the timer bi interrupt control register is set. however, no interrupt request signal is generated when the contents of the counter is transferred first time to the reload register after the count start flag is set to 1. when bit 3 is 1, the pulse width measurement mode is selected. the pulse width measurement mode is similar to the pulse period measurement mode except that the clock is counted from the fall of the tbi in pin input signal to the next rise or from the rise of the input signal to the next fall as shown in figure 34. fig. 31 timer bi mode register bit configuration during event counter mode fig. 30 timer bi mode register bit configuration during timer mode 0 1 : always ?1?in event counter mode 0 : always ??in event counter mode (timer b0) 5 : not used in event counter mode (timers b1, b2) 0 0 : count at the falling edge of input signal 0 1 : count at the rising edge of input signal 1 0 : count at the both falling edge and rising edge of input signal 76543 2 1 0 0 0 55 5 1 timer b0 mode register 5b 16 timer b1 mode register 5c 16 timer b2 mode register 5d 16 addresses 5 5 5 : not used in event counter mode 0 : always ??in timer mode (timer b0) 5 : not used in timer mode (timers b1, b2) 5 : not used in timer mode clock source selection bit 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 timer b0 mode register 5b 16 timer b1 mode register 5c 16 timer b2 mode register 5d 16 addresses 0 0 : always ?0?in timer mode 5 5 : not used in timer mode and may be any 765432 1 0 0 0 0 5 5 5
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 28 when timer bi is read, the contents of the reload register is read. note that, in this mode, the interval from the fall of the tbi in pin input signal to the next rise or from the rise to the next fall must be at least two cycles of the timer count source. timer bi overflow flag which is bit 5 of the timer bi mode register is set to 1 when the timer bi counter reaches 0000 16 . this flag is cleared by writing to the corresponding timer bi mode register. by reading this flag, the reason why the interrupt request signal is generated, which is the completion of measurement or the counter overflow, can be detected. an interrupt request signal may occur because the counter value is particularly undefined just after counting starts. accordingly, make sure to detect the occurrence reason of an interrupt request signal with the timer bi overflow flag. this flag is 1 at reset. when using timer b2 as the clock timer and using timer b1 in the internal connect mode, functions in this mode are lost. fig. 32 timer bi mode register bit configuration during pulse period measurement/pulse width measurement mode fig. 33 pulse period measurement mode operation (example of measuring the interval from the falling edge to next falling one) selected clock source f i tbi in reload register ? counter counter ? 0 count start flag interrupt request signal 76543210 0 1 0 1 0 : always ?0?in pulse period measurement/pulse width measurement mode 0 0 : count from the falling edge of input signal to the next falling one 0 1 : count from the rising edge of input signal to the next rising one 1 0 : count from the falling edge of input signal to the next rising one and from the rising edge to the next falling one 0 : always ??in pulse period measurement/pulse width measurement mode (timer b0) 5 : not used in pulse period measurement/pulse width measurement mode (timers b1, b2) timer bi overflow flag clock source selection bit 0 0 : select f 2 0 1 : select f 16 1 1 : select f 512 1 0 : select f 64 timer b0 mode register 5b 16 timer b2 mode register 5d 16 timer b1 mode register 5c 16 addresses
29 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer fig. 34 pulse width measurement mode operation (4) clock timer when the port-x c selection bit of the oscillation circuit control register 0 (refer to figure 63) is set to 1 to make the sub-clock oscillation circuit active, timer b2 can function as the clock timer, which uses clock f c32 as the clock source. clock f c32 is the sub clock (32 khz) divided by 32. additionally, when the port-xc selection bit is set to 0 not to use the sub-clock and the timer b2 clock source selection bit of the port function control register (refer to figure 11) is set to 1, timer b2 can functions as the clock timer, which uses clock fc 32 as the clock source. clock fc 32 is the main clock divided by 32. figure 35 shows the timer b2 mode register bit configuration when timer b2 is used as the clock timer. as shown in figure 35, the event counter mode must be selected for timer b2. for how to use the clock timer, refer to the section on clock generating circuit. (5) internal connect mode when the timer b1 internal connect selection bit of the port function control register (refer to figure 11) is set to 1, timer b1 uses the timer b2s overflow signal as the clock source and timer b1 is internally connected to timer b2 (cascade connection). the internal connect mode makes timers b1 and b2 function as 16 + 16 bit-timer with the timer b2s clock source. figure 35 shows the timer b1 mode register bit configuration when using timer b1 in the internal connect mode. set timer b1 in the event counter mode as shown in figure 35. fig. 35 timer b1 mode register bit configuration when timer b1 is used in the internal connect mode and timer b2 mode register bit configuration when timer b2 is used as clock timer selected clock source fi tbi in reload register ? counter counter ? 0 count start flag interrupt request signal timer b2 mode register 5d 16 0 1 : always ?1?in event counter mode 0234567 1 555 5 0101 0 1 : count at the rising edge of input signal 5555 : not used in event counter mode address timer b1 mode register 5c 16
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 30 serial i/o ports three independent serial i/o ports are provided. figure 36 shows a block diagram of the serial i/o ports. table 5 shows the functional differences of three serial i/o ports (uart 0, 1, 2). bits 0, 1, and 2 of the uarti (i = 0, 1, 2) transmit/receive mode register shown in figure 37 are used to determine whether to use port p8 or port p10 as a parallel port, a clock synchronous serial i/o port, or an asynchronous serial i/o port (uart) using start and stop bits. fig. 36 serial i/o port block diagram fig. 37 uarti transmit/receive mode register bit configuration uart 0 transmit/receive mode register 30 16 uart 1 transmit/receive mode register 38 16 addresses serial i/o mode selection bits 0 0 0 : parallel port 0 0 1 : clock synchronous 1 0 0 : 7-bit uart 1 0 1 : 8-bit uart 1 1 0 : 9-bit uart 76543 2 1 0 internal clock/external clock selection bit 0 : internal clock 1 : external clock stop bit length selection bit 0 : 1 stop bit 1 : 2 stop bits odd/even parity selection bit 0 : odd parity 1 : even parity parity enable bit 0 : no parity 1 : with parity sleep function selection bit 0 : no sleep 1 : sleep data bus (odd) data bus (even) bit converter 0000000 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 receive register receive buffer register uart0 (addresses 37 16 , 36 16 ) uart1 (addresses 3f 16 , 3e 16 ) uart2 (addresses 6b 16 , 6a 16 ) receive control circuit rxdi data bus (even) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 transmisson register uart0 (addresses 33 16 , 32 16 ) uart1 (addresses 3b 16 , 3a 16 ) uart2 (addresses 67 16 , 66 16 ) control circuit transmission bit converter transmission buffer register polarity reversing circuit f 2 f 16 f 64 f 512 clki ctsi/rtsi 1/16 divider uart receive clock synchronous 1/16 divider clock synchronous 1/2 divider clock synchronous (internal clock) clock synchronous (external clock) 1/(n + 1) divider external internal clock source selection bit rate generator uart0 (address 31 16 ) uart1 (address 39 16 ) uart2 (address 65 16 ) receive clock transmission clock data bus (odd) txdi clock synchronous (internal clock) uart transmission (note) (note) (note) (note) note. uart2 does not include the bit converter, the polarity reversing circuit and the rts i output. uart 2 transmit/receive mode register 64 16 address serial i/o mode selection bits 0 0 0 : parallel port 0 0 1 : clock synchronous 1 0 0 : 7-bit uart 1 0 1 : 8-bit uart 1 1 0 : 9-bit uart 6543 2 1 0 internal clock/external clock selection bit 0 : internal clock 1 : external clock stop bit length selection bit 0 : 1 stop bit 1 : 2 stop bits odd/even parity selection bit 0 : odd parity 1 : even parity parity enable bit 0 : no parity 1 : with parity the switch of a-d conversion interrupt and uart2 transmit/receive interrupt is performed by bits 0 to 2. when selecting a parallel port, a-d conversion interrupt is valid. when selecting a clock synchronous serial i/o port or a uart, uart2 transmit/receive interrupt is valid. note. 7 (note)
31 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer the interrupt vector and the interrupt control register are common to the a-d conversion interrupt and uart2 transmit/receive interrupt. it is switched by a selection of uart2 function as shown in figure 37 and table 5. figure 38 shows the connections of receiver/transmitter. figures 39 and 40 show the bit configuration of the uarti transmit/ receive control register. each communication method is described below. fig. 38 receiver and transmitter block diagram selection of clock synchronous or asynchronous (uart) selection of clock synchronous or asynchronous (uart) selection of clock synchronous or asynchronous (uart) ___ both cts input ___ and rts output ___ both cts input ___ and rts output ___ only cts input transmit and receive (2 systems) transmit and receive (2 systems) transmit/receive (1 system) (note) available available nothing available nothing nothing available available nothing uart0 uart1 uart2 ___ cts input/ ___ rts output communication method selection of data output, clk polarity, transfer format multiple clocks output sleep function interrupt table 5. differences between uart0, uart1 and uart2 note. the interrupt vector and the interrupt control register are common to the a-d conversion interrupt and uart2 transmit/receive interrupt. it is switched by a selection of uart2 function. bit converter d 7 d 0 d 6 d 5 d 4 d 3 d 2 d 1 0 d 8 000 000 rxdi parity bit stop bit stop bit 2 stop bit 1 stop bit parity no parity 7 bit 8 bit 9 bit synchronous synchronous 8 bit 7 bit 7 bit 9 bit synchronous 9 bit 8 bit receive buffer register receive register data bus (odd) data bus (even) bit converter d 7 d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 8 txdi parity bit stop bit parity no parity 7 bit 8 bit 9 bit synchronous 8 bit 7 bit synchronous 9 bit 8 bit transmission buffer register transmission register data bus (odd) data bus (even) synchro- 9 bit 7 bit nous 0 0 stop bit 2 stop bit 1 stop bit (note) (note) transmitter block diagram receiver block diagram note. uart2 does not include the bit converter.
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 32 fig. 39 uart0, uart1 transmit/receive control registers bit configuration uart0 transmit/receive control register 0 34 16 uart1 transmit/receive control register 0 3c 16 addresses tfm cpl txs tx epty r/c cs 1 cs 0 brg count source selection bits 00 : select f 2 01 : select f 16 10 : select f 64 11 : select f 512 cts / rts selection bit 0 : select cts 1 : select rts transmission register empty bit cts , rts enable bit 0 : enble cts and rts 1 : disable cts and rts (i/o port) data output selection bit 0 : cmos output 1 : n-channel open-drain output clk polarity selection bit 0 : in transferring, transmit data is output at the clki's falling edge or received data is input at the clki's rising edge. not in transferring, clki level is "h". 1 : in transferring, transmit data is output at the clki's rising edge or received data is input at the clki's falling edge. not in transferring, clki level is "l". transfer format selection bit 0 : lsb first 1 : msb first 7 654 3210 sum per fer oer ri re ti te transmit enable flag transmit buffer empty flag receive enable bit receive completing flag overrun error flag framing error flag parity error flag error sum flag 7 654 3210 uart0 transmit/receive control register 1 35 16 uart1 transmit/receive control register 1 3d 16 addresses
33 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer fig. 40 uart2 transmit/receive control register bit configuration uart2 transmit/receive control register 0 68 16 addresses tx epty r/c cs 1 cs 0 brg count source selection bits 00 : select f 2 01 : select f 16 10 : select f 64 11 : select f 512 cts enable bit 0 : enable cts 1 : disable cts (i/o port) transmission register empty bit 7 654 3210 sum per fer oer ri re ti te transmit enable flag transmit buffer empty flag receive enable bit receive completing flag overrun error flag framing error flag parity error flag error sum flag 7 654 3210 uart2 transmit/receive control register 1 69 16 addresses
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 34 clock synchronous serial communication a case where communication is performed between two clock synchronous serial i/o ports as shown in figure 41 will be described. (the transmission side will be denoted by subscript j and the receiving side will be denoted by subscript k .) bit 0 of the uart j transmit/receive mode register and uart k transmit/ receive mode register must be set to 1, and bits 1 and 2 must be 0. the length of the transmission data is 8 bits. bit 3 of the uart j transmit/receive mode register of the clock sending side is cleared to 0 to select the internal clock. bit 3 of the uart k transmit/receive mode register of the clock receiving side is set to 1 to select the external clock. bits 4, 5 and 6 are ignored in the clock synchronous mode. bit 7 must always be 0. the clock source is selected by bit 0 (cs 0 ) and bit 1 (cs 1 ) of the clock sending side uart j transmit/receive control register 0. when the contents of the bit rate genarator is n, as shown in figure 36, the selected clock is divided by (n + 1), then by 2, passed through a transmission control circuit, and output as transmission clock clk j . therefore, when the selected clock is f i , bit rate = f i / {(n + 1) 5 2} on the clock receiving side, the cs 0 and cs 1 bits are ignored because an external clock is selected. the bit 2 of the clock sending side uart j transmit/receive control ___ register 0 is cleared to 0 to select cts j input. the bit 2 of the clock ___ receiving side is set to 1 to select rts k output. ___ ___ whether to use signals cts and rts is determined by bit 4 of the ___ uart transmit/receive control register 0. set bit 4 to 0 when cts ___ and rts signals are used, and to 1 when they are not used. ___ ___ uart2 has the cts input function, but that does not have the rts output function (refer to figure 40.) ___ ___ ___ ___ when signals cts and rts are not used, the cts / rts pin can be used as a normal port. the following describes the case when signals ___ ___ ___ ___ cts and rts are used. when signals cts and rts are not used, the ___ ___ cts j input condition is unnecessary and there is no rts k output. output driver format of the transmit data output pin (t x d j ), which is the cmos output or the n-channel open-drain output, is selected with bit 5 (t x s) of the uart j transmit/receive control register 0. when bit 5 is 0, the cmos output format is selected. when bit 5 is 1, the n-channel open-drain output format is selected. when the n-channel open-drain output format is selected, make sure to pull-up the data line using a pull-up resistor. fig. 41 clock synchronous serial communication uart j transmission register uart j transmission buffer register uart j receive buffer register uart j receive register ri per sum fer oer re ti te txd j txd k rxd j rxd k clk j clk k cts j rts k 5 0 55 000 1 uart j transmit/receive mode register 0 tfm cpl txs tx epty 0 cs 1 cs 0 uart j transmit/receive control register 0 uart j transmit/receive control register 1 uart k transmission register uart k transmission buffer register uart k receive buffer register uart k receive register tfm cpl txs tx epty 01 55 fer ri per sum oer re ti te uart k transmit/receive control register 0 uart k transmit/receive control register 1 1 555 000 1 uart k transmit/receive mode register ___ note. uart2 does not include rts output. the uart2 transmit/receive control register 0s bit configuration is partialy different.
35 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer the internal/external clock polarity is selected with bit 6 (cpl) of the uart j transmit/receive control register 0. when bit 6 is 0, transmit data is output at the clk j s falling edge in transmitting, received data is input at the clk k s rising edge in receiving, and the clk i level is h not in transferring (transmitting/receiving). when bit 6 is 1, reversely, transmit data is output at the clk j s rising edge in transmitting, received data is input at the clk k s falling edge in receiving, and the clk i level is l not in transferring. bit transfer order of transmit/received data, which is lsb first or msb first (note), is selected with bit 7 (tfm) of the uart j transmit/receive control register 0. lsb first is selected when bit 7 is 0, and msb first is selected when bit 7 is 1. however, uart2s function is fixed to the function specified by txs=cpl=tfm=0, and it cannot be changed. note that, only in the uart 0 transmission mode, the transmission clock can be output not only from the clk 0 pin but also from the other output pins (clks 0 , clks 1 ). transmission clock output multiple- selection mode is set with the serial transmit control register and others. for details, refer to the section on transmission. note. when lsb first is selected, data is transmitted/received beginning at the least significant bit (lsb). when msb first is selected, data is transmitted/received beginning at the most significant bit (msb). transmission transmission is started when the bit 0 (te j flag) of the uart j transmit/ receive control register 1 is 1, bit 1 (ti j flag) of one is 0, and the ___ cts j input is l. transmit data is output each time when the transmission clock (clk j ) level changes from h to l with bit 6 (cpl) of the uart j transmit/ receive control register 0 0 or is output each time when the clk j level changes from l to h with cpl 1. for details, refer to figure 42. in addition, transmit data is output beginning at the least significant bit (lsb) with bit 7 (tfm) of the uart j transmit/receive control register 0 or is output beginning at the most significant bit (msb) with tfm 1. the ti j flag indicates whether the transmission buffer register is empty or not. it is cleared to 0 when date is written in the transmission buffer register and set to 1 when the contents of the transmission buffer register is transferred to the transmission register. fig. 42 clock synchronous serial i/o timing te j transmission clock (cpl = 0 ) t endj ctsj 1 / f i 5 ( n + 1 ) 5 2 write in transmission buffter register d 0 d 1 d 2 d 3 d 4 d 5 ti j (cpl = 1 ) clk j (tfm = 0 ) (tfm = 1 ) t x d j t x epty j 1 / f i 5 ( n + 1 ) 5 2 stopped because te j = 0 d 6 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 transmission register transmission buffter register
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 36 transmit/receive mode register and the uart0 transmit/receive control register 0/1 in the transmission clock output multiple-selection mode. furthermore, table 6 shows the function of bits 5 and 4 (transmission clock output pin selection bits, tc 1 and tc 0 ) of the serial transmit control register. as shown in table 5, the transmission clock is output from the clk 0 , clks 0 , or clks 1 pin depending on tc 1 , tc 0 . do not change the value of tc 1 and tc 0 during transferring. the transmission clock polarity also depends on bit 6 (cpl) of the uart0 transmit/receive control register 0. when the transmission register becomes empty after its contents has been transmitted, data is automatically transferred from the transmission buffer register to the transmission register if the next transmission start condition is satisfied. when bit 2 of the uart j ___ transmit/receive control register 0 is 1, cts j input is ignored and transmission start is controlled only by the te j flag and ti j flag. once ___ transmission has started, the te j flag, ti j flag, and cts j signals are ignored until data transmission completes. therefore, transmission ___ is not interrupt even when cts j input is changed to h during transmission. ___ as shown in figure 42, cts j and flags te j and ti j , which indicate the transmission start condition, are checked while the t endj signal is h. therefore, data can be transmitted continuously when the next transmission data is written in the transmission buffer register and the ti j flag is cleared to 0 before the t endj signal level becomes h. the bit 3 (t x epty j flag) of the uart j transmit/receive control register 0 changes to 1 at the next cycle after the t endj signal level becomes h. furthermore, the txepty j flag changes to 0 when transmission starts. therefore, this flag can be used to determine whether data transmission has been completed. when the ti j flag changes from 0 to 1, the interrupt request bit in the uart j transmission (transmit/receive in uart2) interrupt control register is set to 1. since uart0 has three output pins (clk 0 , clks 0 , and clks 1 ) for the transmission clock, the user can select one from these pins when using the internal clock. accordingly, data can be transmitted to three external receive devices which will not receive data at the same time. figure 43 shows the extrnal connection diagram example. to select the transmission clock output multiple-selection mode, it is necessary to set bits 5 and 4 of the serial transmit control register. in ___ addition, it is necessary to select the internal clock, to disable cts ___ and rts , and disable reception, with the uart0 transmit/receive mode register and the uart0 transmit/receive control register 0/1. figure 44 shows the bit configuration of the serial transmit control register and figure 45 shows the bit configuration of the uart0 fig. 44 bit configuration of serial transmit control register table 6. relationship between transmission clock output pin selection bits and pin functions transmission clock output pin selection bits 0 0 clk 0 r x d 0 ___ ___ p8/ cts 0 / rts 0 0 1 clk 0 h (note2) p8 0 1 0 h clks 0 p8 0 1 1 h h (note2) clks 1 tc 1 tc 0 p8 1 p8 2 p8 0 r x d 0 ___ ___ cts 0 / rts 0 clk 0 clks 0 clks 1 notes 1. in this table, the clk polarity selection bit (cpl) is 0. when cpl is 1, h in this table becomes l. the polarity of clk 0 , clks 0 , or clks 1 also depends on cpl. 2. when bit 2 of the port p8 direction register is 1, h is output. when this bit is 0, floating is entered. din clk din clk din clk t x d 0 clks 1 clks 0 clk 0 uart 0 note. clock synchronous serial i/o communication and internal clock are used. this connection is applied only in transmission mode. 7 543 21 0 6 serial transmit control register transmission clock output pin selection bits 0 0 : normal mode (clock is output only from clk 0 ) 0 1 : multiple clocks are specified (clock is output from clk 0 ) 1 0 : multiple clocks are specified (clock is output from clks 0 ) 1 1 : multiple clocks are specified (clock is output from clks 1 ) tc 1 tc 0 adress 6e 16 fig. 43 external connection diagram example in the transmission clock output multiple-selection mode
37 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 76543 2 0 1 0 te uart0 transmit/receive control register 1 trasmit enable flag 0 : receiving is disabled 35 16 address uart0 transmit/receive mode register 76543 2 1 0 0 0 5 55 1 0 0 address 30 16 001 : clock synchronous 0 : internal clock 0 : always ? 555 : not used transfer format selection bit 0 : lsb first 1 : msb first aaaaaa 1 : disable cts and rts (i/o port) data output selection bit 0 : cmos output 1 : n-channel open-drain output 76 54 3 2 0 5 1 1 tpm cpl txs cs 1 cs 2 uart0 transmit/receive control register 0 clock source selection bits 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 5 : not used clk polarity selection bit 0 : in transmitting, transmit data is output at the clk's falling edge. not in transmitting, clk 0 level is ?? 1 : in transmitting, transmit data is output at the clk0's rising edge. not in transmitting, clk 0 level is ?? address 34 16 fig. 45 bit configuration of uart0 transmit/receive mode register and uart0 transmit/receive control register 0/1 in the transmission clock output multiple-selection mode receive receive starts when the bit 2 (re k flag) of the uart k transmit/receive control register 1 is set to 1. ___ the rts k output level is h when the re k flag is 0, but it is l when ___ the re k flag is 1 and the ti k flag is 0. furthermore, the rts k output level is h again when receiving restarts. the ti k flag is cleared to 0 by writing dummy data into the transmission buffer register. when ___ the rts k output level is l, receiving for the receive register is enabled. ___ uart2 does not have the rts output function. when bit 6 (cpl) of the uart k transmit/receive control register 0 is 0, the contents of the receive register is shifted by 1 bit each time when the receive clock (clk k ) changes from l to h. when cpl is 1, the contents is shifted by 1 bit each time when clk k changes from h to l. these shifts are performed simultaneously with the data reception from the r x d k pin. when an 8-bit data is received, the contents of the receive register is transferred to the receive buffer register and the bit 3 (ri k flag) of the uart k transmit/receive control register 1 is set to 1. in other words, the setting of the ri k flag to 1 indicates that the receive buffer register contains the received data. ___ when the ti k flag goes 0, rts k output level goes l to indicate that the next data can be received. when the ri k flag changes from 0 to 1, the interrupt request bit of the uart k receive (transmit/receive in uart2) interrupt control register is set to 1. bit 4 (oer k flag) of the uart k transmit/receive control register is set to 1 when the next data is transferred from the receive register to the receive buffer register while ri k flag is 1, and the oer k flag indicates that the next data was transferred to the receive buffer register before the contents of the receive buffer register was read. the ri k flag is cleared to 0 when reading the low-order byte to the receive buffer, when writing 0 to the re k flag, or when setting to be a parallel port. the oer k flag is cleared to 0 when writing 0 to the re k flag or when setting to be a parallel port. the fer k , per k , and sum k flags are ineffective in the clock synchronous communication. the received data in the receive buffer register is read into the data bus according to the lsb first (beginning at the least significant bit) when bit 7 (tem) of the uart k transmit/receive control register 0 is 0 or according to the msb first (beginning at the most significant bit) when bit 7 is 1. as shown in figure 36, with clock synchronous serial communication, data cannot be received unless the transmitter is operating because the receive clock is created from the transmission clock. therefore, the transmitter must be operating even when there is no data to be sent from uart k to uart j .
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 38 asynchronous serial communication (uart) asynchronous serial communication can be performed using 7-, 8-, or 9-bit length data. the operation is the same for all data lengths. the following is the description for 8-bit asynchronous communication. with 8-bit asynchronous communication, the bits 2 to 0 of the uart i transmit/receive mode register must be 101. bit 3 is used to select an internal clock or an external clock. when bit 3 is 0, an internal clock is selected and when bit 3 is 1, then external clock is selected. when an internal clock is selected, the bit 0 (cs 0 ) and bit 1 (cs 1 ) of uart i transmit/receive control register 0 are used to select the clock source. when an internal clock is selected for asynchronous serial communication, the clk i pin can be used as a normal port. when the content of the bit rate generator is n, the selected internal or external clock is divided by (n + 1), then by 16, and passed through a control circuit to create the uart transmission clock or the uart receive clock. when the selected clock is an internal clock fi or an external clock f ext , bit rate = (fi or f ext ) / {(n + 1) 5 16} bit 4 selects 1 stop bit or 2 stop bits. the bit 5 is a selection bit of odd parity or even parity. in the odd parity mode, the parity bit is adjusted so that the sum of the 1s in the data and parity bit is always odd. in the even parity mode, the parity bit is adjusted so that the sum of the 1s in the data and parity bit is always even. fig. 47 transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits is selected fig. 46 transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit is selected d 6 d 7 st d 1 d 2 d 3 d 4 d 5 p sp st st d 0 d 1 te i (1 / f 1 , or 1 / f ext ) 5 (n + 1) 5 16 transmission clock cts i write in transmission buffer register ti i t endi t x d i t x epty i transmission register ? transmission buffer register stopped because tei = 0 start bit parity bit stop bit d 0 d 6 d 7 d 1 d 2 d 3 d 4 d 5 p sp d 0 te i transmission clock ti i t endi t x d i t x epty i (1 / f 1 , or 1 / f ext ) 5 (n + 1) 5 16 write in transmission buffer register transmission register ? transmission buffer register stopped because start bit stop bit stop bit tei = 0 d 6 st d 1 d 2 d 3 d 4 d 5 d 8 sp st d 0 d 1 d 0 d 6 d 7 d 1 d 2 d 3 d 4 d 5 sp d 0 d 7 sp sp d 8 st d 2
39 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer bit 6 is the parity enable bit which indicates whether to add parity bit or not. bits 4 to 6 should be set or reset according to the data format of the communicating devices. bit 7 is the sleep selection bit (refer to the next page). bit 2 of the uart i transmit/receive control register 0 is used to ___ ___ ___ determine whether to use cts i input or rts i output. cts i input is used ___ if bit 2 is 0 and rts i output is used if bit 2 is 1. ___ if cts i input is selected, the user can control whether to stop or start ___ transmission with external cts i input. ___ ___ whether to use cts and rts signals is determined by bit 4 of the ___ uart transmit/receive control register 0. set bit 4 to 0 when cts ___ and rts signals are used, and to 1 when they are not used. ___ ___ uart2 has the cts input function, but that does not have the rts output function (refer to figure 40.) ___ ___ ___ ___ when cts and rts signals are not used, the cts / rts pin can be used as a normal port. the following describes the case when the ___ ___ ___ ___ cts and rts signals are used. if cts and rts signals are not used, ___ ___ the cts i input condition is unnecessary and there is no rts i output. in addition, output driver format of the transmission data output pin (t x d j ), which is cmos output or n-channel open-drain output, is selected with bit 5 (t x s) of the uart j transmit/receive control register 0. cmos output format is selected when bit 5 is 0, and n-channel open-drain output format is selected when bit 5 is 1. when n-channel open-drain output format is selected, make sure to pull-up the data line using a pull-up resistor. however, uart2 does not have bit 5 (txs) and the format is always cmos output. in asynchronous serial communication, bits 6 and 7 of the uart j transmit/receive control register 0 must be 0. transmission transmission is started when the bit 0 (te i flag) of uart i transmit/ ___ receive control register 1 is 1, the bit 1 (ti i flag) is 0, and cts i input ___ is l if cts i input is selected. as shown in figures 46 and 47, data is output from the t x d i pin with the start bit and the stop bit or parity bit specified by the bits 4 to 6 of uart i transmit/receive mode register. the data is output beginning at the least significant bit. the ti i flag indicates whether the transmission butter is empty or not. it is cleared to 0 when data is written in the transmission buffer and set to 1 when the contents of the transmission buffer register is transferred to the transmission register. when the transmission register becomes empty after the contents has been transmitted, data is transferred automatically from the transmission buffer register to the transmission register if the next transmission start condition is satisfied. ___ once transmission has started, the te i flag, ti i flag, and cts i signal ___ (if cts i input is selected) are ignored until data transmission is completed. therefore, transmission does not stop until it completes even if the te i flag is cleared during transmission. ___ as shown in figure 46, cts i input and flags te i and ti i , which indicate the transmission start condition, are checked while the t endi signal is h. therefore, data can be transmitted continuously if the next transmission data is written in the transmission buffer register and ti i flag is cleared to 0 before the t endi signal goes h. the bit 3 (t x epty i flag) of the uart i transmit/receive control register 0 changes to 1 at the next cycle after the t endi signal goes h and changes to 0 when transmission starts. therefore, this flag can be used to determine whether data transmission is completed. when the tii flag changes from 0 to 1, the interrupt request bit of the uart i transmission (transmit/receive in uart2) interrupt control register is set to 1.
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 40 receive receive is enabled when bit 2 (re i flag) of the uart i transmit/receive control register 1 is set to 1. as shown in figure 48, the frequency divider circuit at the receiving end begin to work when a start bit is arrived and the data is received. ___ if rts i output is selected by setting bit 2 of the uart i transmit/receive ___ control register 0 to 1, the rts i output is h when the re i flag is 0. ___ when the re i flag changes to 1, the rts i output goes l to indicate receive ready and returns to h once receive has started. in other ___ words, rts i output can be used to determine externally whether the ___ receive register is ready to receive. (uart2 does not have the rts output function.) the entire transmission data bits are received when the start bit passes the final bit of the receive register of the receive block shown in figure 38. at this point, the contents of the receive register is transferred to the receive buffer register and the bit 3 of the uart i transmit/receive control register 1 (ri i flag) is set. in other words, the ri i flag indicates that the receive buffer register contains data when it ___ ___ is set. if rts i output is selected, rts i output goes l to indicate that the register is ready to receive the next data. the interrupt request bit of the uart i receive (transmit/receive in uart2) interrupt control register is set when the ri i flag changes from 0 to 1. the bit 4 (oer i flag) of the uart i transmission control register 1 is set when the next data is transferred from the receive register to the receive buffer register while the ri i flag is 1. in other words when an overrun error occurs. if the oer i flag is 1, it indicates that the next data has been transferred to the receive buffer register before the contents of the receive butter register has been read. bit 5 (fer i flag) is set when the number of stop bits is less than required (framing error). bit 6 (per i flag) is set when a parity error occurs. bit 7 (sum i flag) is set when either the oer i flag, fer i flag, or the per i flag is set. therefore, the sum i flag can be used to determine whether there is an error. the setting of the ri i flag, oer i flag, fer i flag, and the per i flag is performed while transferring the contents of the receive register to the receive buffer register. the ri i , fer i , and per i flags are cleared when reading the low-order byte of the receive buffer register or when writing 0 to the re i flag or when setting to be a parallel port. the oer i and sum i flags are cleared when writing 0 to the re i flag or when the setting to be a parallel port. sleep mode the sleep mode is used to communicate only between certain microcomputers when multiple microcomputers are connected through serial i/o. the sleep mode is entered when bit 7 of the uart i transmit/receive mode register is set to 1. uart2 does not have the sleep mode. the operation of the sleep mode for an 8-bit asynchronous communication is described below. when sleep mode is selected, the contents of the receive register is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asynchronous communication and bit 8 if 9-bit asychronous communication) of the received data is 0. also the ri i , oer i , fer i , per i , and the sum i flag are unchanged. therefore, the interrupt request bit of the uart i receive interrupt control register is also unchanged. normal receive operation takes place when bit 7 of the received data is 1. the following is an example of how the sleep mode can be used. the main microcomputer first sends data with bit 7 set to 1 and bits 0 to 6 set to the address of the subordinate microcomputer which wants to communicate with. then all subordinate microcomputers receive the same data. each subordinate microcomputer checks the received data, clears the sleep function selection bit if bits 0 to 6 are its own address and sets the sleep bit if not. next the main microcomputer sends data with bit 7 cleared. then the microcomputer with the sleep bit cleared will receive the data, but the microcomputer with the sleep bit set will not. in this way, the main microcomputer is able to communicate only with the designated microcomputer. fig. 48 receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit is selected f i or f ext d 0 re i r x d i receive clock ri i rts i start bit d 1 stop bit d 7 start bit starting at the falling edge of start bit check to be ??level get data
41 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer a-d converter the a-d converter is an 10-bit successive approximation converter. figure 49 shows a block diagram of the a-d converter and figure 50 shows the configuration of the a-d control register 0 (address 1e 16 ) and a-d control register 1 (address 1f 16 ). the frequency of the a-d converter operating clock ad is selected by bit 7 of the a-d control register 0. when bit 7 is 0, ad is the clock frequency divided by 4. that is, ad = f 2 /4. when bit 7 is 1, ad is the clock frequency divided by 2 and ad = f 2 /2. the ad during a-d conversion must be 250 khz or more because the comparator uses a capacity coupling amplifier. bit 3 of a-d control register 1 is used to select whether to use the conversion result as 10 bits or as 8 bits. the conversion result is used as 10 bits when bit 3 is 1 and as 8 bits when bit 3 is 0. when the conversion result is used as 10 bits, the low-order 8 bits of the conversion result is stored in the even address of the corresponding a-d register and the high-order two bits are stored in bits 0 and 1 of the odd address of the corresponding a-d register. bits 2 to 7 of the a-d register odd address return 000000 2 when read. when the conversion result is used as 8 bits, the high-order 8 bits of the 10-bit a-d conversion are stored in even address of the corresponding a-d register. in this case, the a-d register odd address returns 00 16 when read. the operating mode is selected by bits 3 and 4 of a-d control register 0. the available operating modes are one-shot, repeat, single sweep, repeat sweep. whether to connect the reference voltage input pin (v ref ) with the ladder network or not depends on bit 5 of the a-d control register 1. the v ref pin is connected when bit 5 is 0 and is disconnected when bit 5 is 1 (high impedance state). when a-d conversion is not performed, current from the v ref pin to the ladder network can be cut off by disconnecting ladder network from the v ref pin. before starting a-d conversion, wait for 1 s or more after clearing bit 5 to 0. the bit of the port direction register corresponding to the analog input pin to be used must be 0 (input mode) because the analog input pin is also used as port p7. note that when using the sub-clock (x cin - x cout ) or uart2, the analog pins shared with those functions cannot be used. the operation of each mode is described below. the interrupt vector and the interrupt control register are common to the a-d conversion interrupt and uart2 transmit/receive interrupt. it is switched by a selection of uart2 function as shown in figure 37s note. fig. 49 a-d converter block diagram data bus (odd) data bus (even) selector an 0 an 1 an 2 an 3 an 4 an 5 /ad trg an 6 an 7 ladder network v ref successive approximation register address address 1/2 f 2 1/2 a-d register 0 (21 16 ) a-d register 1 (23 16 ) a-d register 2 (25 16 ) a-d register 3 (27 16 ) a-d register 4 (29 16 ) a-d register 5 (2b 16 ) a-d register 6 (2d 16 ) a-d register 7 (2f 16 ) a-d register 0 (20 16 ) a-d register 1 (22 16 ) a-d register 2 (24 16 ) a-d register 3 (26 16 ) a-d register 4 (28 16 ) a-d register 5 (2a 16 ) a-d register 6 (2c 16 ) a-d register 7 (2e 16 ) decoder comparator a-d control register 1 (1f 16 ) a-d control register 0 (1e 16 ) v ref av ss v ref connect selection ad selection ad
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 42 (1) one-shot mode one-shot mode is selected when bits 3 and 4 of a-d control register 0 are 0. the analog input pin (an 0 C an 7 ) is selected with bits 0 to 2 of a-d control register 0. a-d conversion can be started by a software trigger or by an external trigger. a software trigger is selected when bit 5 of a-d control register 0 is 0 and an external trigger is selected when it is 1. when a software trigger is selected, a-d conversion is started when bit 6 (a-d conversion start flag) is set to 1. a-d conversion ends after 59 ad cycles and an interrupt request bit of the a-d conversion interrupt control register is set to 1. at the same time, the a-d conversion start flag (bit 6 of the a-d control register 0) is cleared and a-d conversion stops. the result of a-d conversion is stored in the a-d register corresponding to the selected pin. if an external trigger is selected, a-d conversion starts when the a-d ____ conversion start flag is 1 and the ad trg input changes from h to l. in this case, the pins that can be used for a-d conversion are ____ an 0 to an 4 , an 6 and an 7 (a total of 7) because the ad trg pin is also used as the analog voltage input pin (an 5 ). the operation is the same as with software trigger except that the a-d conversion start flag is not cleared after a-d conversion and a retrigger can be available during a-d conversion. (2) repeat mode repeat mode is selected when bit 3 of a-d control register 0 is 1 and bit 4 is 0. the operation of this mode is the same as the operation of one-shot mode except that when a-d conversion of the selected pin is complete and the result is stored in the a-d register, conversion does not stop, but is repeated. no interrupt request is issued in this mode. furthermore, if software trigger is selected, the a-d conversion start flag is not cleared. the contents of the a-d register can be read at any time. fig. 50 a-d control register bit configuration 765432 0 1 0 address 1f 16 a-d control register 1 a-d sweep pin selection bits 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 C an 3 (4 pins) 1 0 : an 0 C an 5 (6 pins) 1 1 : an 0 C an 7 (8 pins) 0 : always 0 v ref connection selection bit 0 : v ref is connected 1 : v ref is not connected analog input selection bits 0 0 0 : select an 0 0 0 1 : select an 1 0 1 0 : select an 2 0 1 1 : select an 3 1 0 0 : select an 4 1 0 1 : select an 5 1 1 0 : select an 6 1 1 1 : select an 7 a-d operation mode selection bits 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 765432 0 1 a-d control register 0 trigger selection bit 0 : software trigger 1 : ad trg input trigger a-d conversion start flag 0 : stop a-d conversion 1 : start a-d conversion a-d conversion frequency ( ad ) selection flag 0 : select f 2 /4 1 : select f 2 /2 1e 16 address 8/10-bit mode selection bit 0 : 8-bit mode 1 : 10-bit mode
43 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer (3) single sweep mode single sweep mode is selected when bit 3 of a-d control register 0 is 0 and bit 4 is 1. in the single sweep mode, the number of analog input pins to be swept can be selected. analog input pins are selected by bits 1 and 0 of the a-d control register 1 (address 1f 16 ). two pins, four pins, six pins or eight pins can be selected as analog input pins, depending on the contents of these bits. a-d conversion is performed only for selected input pins. after a-d conversion is performed for input of an 0 pin, the conversion result is stored in a-d register 0, and in the same way, a-d conversion is performed for selected pins one after another. after a-d conversion is performed for all selected pins, the sweep is stopped. a-d conversion can be started with a software trigger or with an external trigger input. a software trigger is selected when bit 5 is 0 and an external trigger is selected when it is 1. when a software trigger is selected, a-d conversion is started when a-d control register 0 bit 6 (a-d conversion start flag) is set to 1. when a-d conversion of all selected pins ends, an interrupt request bit of the a-d conversion interrupt control register is set to 1. at the same time, a-d conversion start flag is cleared and a-d conversion stops. if an external trigger is selected, a-d conversion starts when the a-d ____ conversion start flag is 1 and the ad trg input changes from h to l. in this case, the a-d conversion result which is stored in the a-d ____ register 5 becomes invalid because the ad trg pin is also used as the an 5 pin. the operation by external trigger is the same as that done by software trigger except that the a-d conversion start flag is not cleared after a-d conversion and a retrigger can be available during a-d conversion. (4) repeat sweep mode repeat sweep mode 0 is selected when bit 3 of a-d control register 0 is 1 and bit 4 is 1. the difference from the single sweep mode is that a-d conversion does not stop after converting from the an 0 pin to the selected pins, but repeats again from the an 0 pin. the repeat is performed among the selected pins. also, no interrupt request is generated. furthermore, if software trigger is selected, the a-d conversion start flag is not cleared. the a-d register can be read at any time.
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 44 watchdog timer the watchdog timer is used to detect unexpected execution sequence caused by software runaway. figure 51 shows a block diagram of the watchdog timer. the watchdog timer includes a 12-bit binary counter. the watchdog timer counts divided clock f 32 or f 512 . whether to count f 32 or f 512 is determined by the watchdog timer frequency selection flag shown in figure 52. for divided clocks f 32 and f 512 , refer to the section on clock generating circuit. f 512 is selected when the flag is 0 and f 32 is selected when it is 1. the flag is cleared after reset. fff 16 is set in the watchdog timer when l or 2 vcc is applied to _____ the reset pin, stp instruction is executed, data is written to the watchdog timer register, or the most significant bit of the watchdog timer becomes 0. after fff 16 is set in the watchdog timer, the contents of the watchdog timer is decremented by one at every cycle of f 32 or f 512 . after 2048 counts, the most significant bit of the watchdog timer becomes 0, and a watchdog timer interrupt request bit is set, and fff 16 is set in the watchdog timer. normally, a program is written so that data is written in the watchdog timer register before the most significant bit of the watchdog timer becomes 0. if this routine is not executed due to unexpected program runaway, the most significant bit of the watchdog timer becomes eventually 0 and an interrupt is generated. the processor can be reset by setting 1 to the software reset bit (bit 3 of the processor mode register 0) described in figure 10 on the interrupt section and generating a reset pulse. _____ the watchdog timer stops its function when the reset pin voltage is raised to double the vcc voltage. the watchdog timer can also be used to recover from when the clock is stopped by the stp instruction. refer to the section on stand-by function for more details. the watchdog timer hold the contents during a hold state and the input of the divided clock is stopped. fig. 51 watchdog timer block diagram fig. 52 watchdog timer frequency selection flag 0 : select f 512 1 : select f 32 7 61 16 addresses watchdog timer frequency selection flag 6 5 4 3 2 1 0 select with the watchdog timer frequency selection flag. (if stp instruction is executed, f 32 is forced to be selected when the system clock selection bit is ?? or f 8 is forced to be selected when the system clock selection bit is ??) set ?ff 16 write to watchdog timer register detection 2 ?vcc circuit sq r reset stp instruction f 512 f 32 watchog timer hold (address 60 16 ) note. when the main clock external input selection bit is ?? and the main clock or the main clock divided by 8 is selected as a system clock, or the sub-clock external input selection bit is ??and the sub-clock is selected; the divided clock f 16 is input. (note)
45 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer reset circuit _____ the microcomputer is released from the reset state when the reset pin is returned to h level after holding it at l level with the power source voltage at 5 v 10%. program execution starts at the address formed by setting address a 23 C a 16 to 00 16 , a 15 C a 8 to the contents of address ffff 16 , and a 7 C a 0 to the contents of address fffe 16 . figure 53 shows the status of the internal registers during reset. fig. 53 microcomputer internal status during reset address 00 16 0000 00 16 00 16 00 16 00 16 00 16 00 16 0 11 00 00 0 0 ??? 00 16 00 16 0 00 00 00 00 00 00 00 00 10 00 00 10 00 00 10 10 00 16 000 0 0 00 16 00 16 00 16 00 16 00 16 00 16 0 001 00 0 0 001 001 00 0 0 00 0 0 0 00 16 (04 16 ) (05 16 ) (08 16 ) (09 16 ) (0c 16 ) (0d 16 ) (10 16 ) (11 16 ) (14 16 ) (1e 16 ) (1f 16 ) (30 16 ) (38 16 ) (34 16 ) (3c 16 ) (35 16 ) (3d 16 ) (40 16 ) (42 16 ) (44 16 ) (56 16 ) (57 16 ) (58 16 ) (59 16 ) (5a 16 ) (5b 16 ) (5c 16 ) (5d 16 ) (5e 16 ) (5f 16 ) port p0 direction register port p1 direction register port p2 direction register port p3 direction register port p4 direction register port p5 direction register port p6 direction register port p7 direction register port p8 direction register a-d control register 0 a-d control register 1 uart 0 transmit/receive mode register uart 1 transmit/receive control register 1 uart 1 transmit/receive mode register uart 0 transmit/receive control register 0 uart 1 transmit/receive control register 0 uart 0 transmit/receive control register 1 count start flag one- shot start flag up-down flag timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 processor mode register 1 address (60 16 ) (7f 16 ) (6c 16 ) (6d 16 ) (6e 16 ) (6f 16 ) (70 16 ) (71 16 ) (72 16 ) (73 16 ) (74 16 ) (75 16 ) (76 16 ) (77 16 ) (78 16 ) (79 16 ) (7a 16 ) (7b 16 ) (7c 16 ) (7d 16 ) (7e 16 ) watchdog timer register oscillation circuit control register 0 port function control register serial transmit control register oscillation circuit control register 1 a-d/uart2 trans./rece. interrupt control register uart 0 transmission interrupt control register uart 0 receive interrupt control register uart 1 transmission interrupt control register uart 1 receive interrupt control register timer a0 interrupt control register timer b2 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register processor status register (ps) program bank register (pg) program counter (pc h ) program counter (pc l ) direct page register (dpr) data bank register (dt) int 0 interrupt control register 0 0 0 contents of other registers and ram are undefined during reset. initialize them by software. ? 0 0 0 0000 0 ? 001 000 000 000 000 1?? 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 0 0 0 00 00 0 0 0 00 16 00 16 contents of ffff 16 contents of fffe 16 0000 16 fff 16 0 0 0 0 0 0 int 1 interrupt control register int 2 /key input interrupt control register 00 16 0 01 0 00 00 (61 16 ) (63 16 ) (64 16 ) (68 16 ) watchdog timer frequency selection flag memory allocation control uart2 transmit/receive mode register uart2 transmit/receive control register 0 0 0 0 001 0 00 0 00 0 0 (69 16 ) uart2 transmit/receive control register 1 0000 0 00 000 1 0010 0 00 0 00 16 0 00 16 (18 16 ) port p10 direction register
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 46 input / output pins ports p0 to p8, p10 all have a port direction register and each bit can be programmed for input or output. a pin becomes an output pin when the corresponding bit of the port direction register is set to 1 and an input pin when the bit is cleared to 0. when a pin is programmed for output, the data is written to the port latch and is output, and the contents of the port latch is read instead of the value of the pin. therefore, a previously output value can be read correctly even when the output l voltage is raised by directly driving an led or others. a pin programmed for input is floating and the value input to the pin can be read. when a pin is programmed for input, the data is written only in the port latch and the pin retains floating. ports p6 2 to p6 4 , and p10 4 to p10 7 , however, have pull-up transistors and the ports pull-up function can be selected by setting 1 to bits 6, 5, 3 of the port function control register (reffer to figure 11.) a port which corresponds to a port direction registers bit set to 0 is pulled up. a port which corresponds to a bit set to 1 is an output pin and it is not pulled up. port p9 is output exclusive pin. this becomes floating at reset. the contents are output at finishing data write to the port p9 latch. after that, even when changing the data of the port p9 latch, that port cannot be floating. figures 55 and 56 show the block diagram of ports p0 to p10 and _ the e pin output format. in the memory expansion mode and the microprocessor mode, ports p0 to p4 are also used as address, data, and control signal pins. refer to the section on the processor modes for more details. figure 54 shows an example of a reset circuit. if the stabilized clock is input from the external to the main-clock oscillation circuit, the reset input voltage must be 0.9 v or less when the power source voltage reaches 4.5 v. if a resonator/oscillator is connected to the main-clock oscillation circuit, change the reset input voltage from l to h after the main-clock oscillation is fully stabilized. v cc reset reset v cc 0v 0v 4.5v 0.9v power on note. in this case, stabilized clock is input from the external to the main-clock oscillation circuit. perform careful evaluation at the system design level before using. fig. 54 example of a reset circuit
47 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer _ fig. 55 block diagram for ports p0 to p10 and the e pin output format (1) ?ports p0 0 ?p0 7 , p1 0 ?p1 7 , p2 0 ?p2 7 , p3 0 ?p3 3 , p4 3 ?p4 6 , p10 0 ?p10 3 (inside dotted-line not included) ports p4 0 , p4 1 , p4 7 , p5 1 , p5 3 , p5 5 , p5 7 , p6 1 , p6 5 ?p6 7 , p8 6 (inside dotted-line included) data bus port direction register port latch valid only when pins are used as txd j pins for serial i/o communication ?ports p8 3 , p8 7 (inside dotted-line not included. shaded area included.) ports p5 0 , p5 2 , p5 4 , p5 6 , p6 0 , p8 2 (inside dotted-line included. shaded area not included.) port p4 2 (inside dotted-line not included. shaded area not included.) data bus ? output n-channel open-drain selection (note 1) port latch port direction register ?ports p6 2 ?p6 4 (inside dotted-line included.) ?ports p10 4 ?p10 7 (inside dotted-line not included.) pull-up selection port latch port direction register data bus pull-up transistor note 1. data bus ?ports p7 0 ?p7 7 port latch port direction register analog input sub-clock oscillation circuit (note 2) note 2. only p7 6 , p7 7 as sub-clock oscillation circuit
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 48 _ fig. 56 block diagram for ports p0 to p10 and the e pin output format (2) ? ports p9 0 , p9 2 (inside dotted-line included.) ? ports p9 4 C p9 7 (inside dotted-line not included.) ? ports p8 0 , p8 1 , p8 4 , p8 5 data bus 1 output 0 port direction register port latch data bus port latch output control ? port p9 1 (inside dotted-line included.) ? port p9 3 (inside dotted-line not included.) data bus output port latch output control hold acknowledge (b) (a) external bus mode ? e 0
49 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer processor mode bits 0 and 1 of processor mode register 0 shown in figure 57 are used to select any mode of the single-chip mode, the memory expansion mode, the microprocessor mode and the evaluation mode. ports p0 to p3 and a part of port p4 are used as i/o pins of address, data, and control signals except for in the single-chip mode. as the combination of these address, data, and control signals, either of 2 types (external bus mode a or external bus mode b) can be selected. figures 58 and 59 show the functions of ports p0 to p4 in each external bus mode. the external memory area changes when the processor mode changes. figure 60 shows the memory map for each processor mode. refer to figure 1 for the addresses of ram and rom. the external memory area can be accessed except in the single-chip mode. the accessing of the external memory is affected by the byte pin, the wait bit (bit 2 of the processor mode register 0), and the wait selection bit (bit 0 of the processor mode register 1). these will be described next. ?external bus mode the external bus mode (external bus mode a and external bus mode b) to access an external memory can be selected by the level of the bsel pin. when the level of the bsel pin is h, the external bus mode a (see figure 58) is selected. when the level of the bsel pin is l, the external bus mode b (see figure 59) is selected. ?byte pin when accessing the external memory, the level of the byte pin is used to determine whether to use the data bus as 8-bit width or 16- bit width. the data bus has a width of 8 bits when level of the byte pin is h, and port p2 becomes the data i/o pin. the data bus has a width of 16 bits when the level of the byte pin is l, and ports p1 and p2 become the data i/o pins. when accessing the internal memory, the data bus always has a width of 16 bits regardless of the byte pin level. fig. 57 processor mode register bit configuration clock 1 output selection bit 0 : no 1 output 1 : 1 output processor mode bit 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode 1 1 : evaluation mode wait bit 0 : wait 1 : no wait software reset bit reset occurs when this bit is set to 1 interrupt priority detection time selection bit 0 0 : internal clock 5 7 (cycle) 0 1 : internal clock 5 4 (cycle) 1 0 : internal clock 5 2 (cycle) test mode bit this bit must be "0" 765432 0 1 0 processor mode register 0 address 5e 16 address 5f 16 processor mode register 1 wait selection bit 0 : wait 0 1 : wait 1 765432 0 1
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 50 [external bus mode a] pm 1 0 0 0 1 1 0 1 1 single-chip mode memory expansion mode evaluation chip mode microprocessor mode same as left same as left same as left same as left same as left same as left same as left same as left same as left same as left pm 0 mode e (note) i/o port i/o port i/o port i/o port i/o port in this case, bit 7 of the processor mode register 0 is 0 in this case, bit 7 of the processor mode register 0 is 0 in this case, bit 7 of the processor mode register 0 is 1 in this case, bit 7 of the processor mode register 0 is 1 p0 7 p0 0 port port p0 port p3 port p4 port p1 port p2 byte =l byte =h byte =l byte =h ~ e (note) address a 7 ~a 0 p0 7 a 15 ~a 8 p0 0 ~ e address data(odd) p1 7 p1 0 ~ p1 7 p1 0 ~ e address ports p4, p5 and their direction registers are treated as 16-bit wide bus. ports p4, p5 and their direction registers are treated as 16-bit wide bus. data(odd) p1 7 p1 0 ~ e p2 7 p2 0 ~ e p2 7 p2 0 ~ e p3 3 p3 0 ~ e p4 7 p4 0 p4 2 11 ~ e i/o port p4 7 p4 2 p4 1 p4 0 p4 2 ~ e p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 e e address a 15 ~a 8 p1 7 p1 0 ~ e address data (even) address data (even, odd) p2 7 p2 0 ~ e p2 7 p2 0 ~ e p3 3 hlda ale p3 2 p3 1 p3 0 a 23 ~a 16 a 23 ~a 16 a 15 ~a 8 address data (even, odd) a 23 ~a 16 hold bhe dbc vpa vda qcl mx 1 rdy hold r /w rdy same as above except p4 2 same as above except p4 2 same as left except for port p4 2 which out- puts 1 inde- pendent of bit 7 of the pro- cessor mode register 0 (note) fig. 58 relationship between ports p0 to p4 and processor modes (external bus mode a) note. _ the signal output disable selection bit (bit 6 of the oscillation circuit control register 0) can stop the e signal output in the single-chip _ mode and the 1 output in the microprocessor mode. in the memory expansion mode or the microprocessor mode, signal e can also be fixed to h when the internal memory area is accessed.
51 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer [external bus mode b] _ ___ fig. 59 relationship between ports p0 to p4, e / rde pin, and processor modes (external bus mode b) notes 1. _ in the memory expansion mode or the microprocessor mode, signal e is not output. 2. _ the signal output disable selection bit (bit 6 of the oscillation circuit control register 0) can stop signal e output in the single-chip mode ___ ___ and the 1 output in the microprocessor mode. in the memory expansion mode or the microprocessor mode, signals rde , wel , ___ weh can also be fixed to h when the internal memory area is accessed. 3. in the external bus mode b, the evaluation chip mode cannot be selected. ale hlda i/o port i/o port i/o port i/o port address data(odd) address a 8 to a 15 address data(even) address (odd,even) i/o port pm 1 pm 0 mode 0 0 0 1 1 0 single-chip mode memory expansion mode microprocessor mode (note 1) (note 2) port e/rde port p0 port p1 port p2 byte = l byte = h byte = l byte = h port p3 port p4 e p0 0 to p0 7 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 3 p4 0 to p4 7 p4 2 (note 2) (note 1) 1 p4 2 1 rde address a 16, a 17 p0 6 p0 7 p1 0 to p1 7 p1 0 to p1 7 p2 0 to p2 7 p2 0 to p2 7 p3 0 p3 1 p3 2 p3 3 p4 0 p4 1 p4 2 to p4 7 ? in this case, bit 7 of the processor mode register 0 is 0 ? in this case, bit 7 of the processor mode register 0 is 0 same as above excep t p4 2 ? in this case, bit 7 of the processor mode register 0 is 1 same as above except p4 2 ? in this case, bit 7 of the processor mode register 0 is 1 same as left same as left same as left same as left same as left same as left same as left same as left except for port p4 2 which outputs 1 independent of bit 7 of the processor mode register 0 rsmp (note 2) weh wel hold i/o port p0 5 cs 0 C cs 4 p0 0 to p0 4 a 8 to a 15 e e e e e e e e e e e e e rdy data a 0 to a 7 a 0 to a 7 (note 2)
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 52 fig. 61 relationship between wait bit, wait selection bit, and access time ?wait bit as shown in figure 61, when the external memory area is accessed with the wait bit (bit 2 of the processor mode register 0 at address 5e 16 ) cleared to 0, the access time can be extended compared with no wait (the wait bit is 1). the access time is extended in two ways and this is selected with the wait selection bit (bit 0 of the processor mode register 1 at address 5f 16 ). when this bit is 1, the access time is 1.5 times compared to that for no wait. when this bit is 0, the access time is twice compared to that for no wait. at reset, the wait bit and the wait selection bit are 0. the accessing of internal memory area is always performed in the no wait mode regardless of the wait bit. the processor modes are described below. wait bit 1 (no wait) wait bit 0 (wait 1) wait bit 0 (wait 0) internal clock port p2 ale port p2 ale access time access time address data address data address data address data port p2 ale access time address data address sfr ram microprocessor mode the shaded area is the external memory area. sfr 00 16 80 16 ffffff 16 ram rom memory expansion mode 1000 16 1ffff 16 fff 16 sfr ram evaluation chip mode 2 16 c 16 a 16 e or rde, wel,weh e or rde, wel,weh e or rde, wel,weh fig. 60 external memory area for each processor mode (1) single-chip mode [00] single-chip mode is entered by connecting the cnvss pin to vss and starting from reset. ports p0 to p4 all function as normal i/o ports. port p4 2 can output clock 1 by setting bit 7 of the processor mode register 0 to 1. for clock 1 , refer to figure 66. _ _ ___ _ in this mode, signal e is output from pin e/rde . signal e output, however, can be stopped by setting the signal output disable selection bit (bit 6 of the oscillation circuit control register 0) to 1, and it is _ possible to switch the e pin function to l output. table 7 shows the function of the signal output disable selection bit. (2) memory expansion mode [01] memory expansion mode is entered by setting the processor mode bits to 01 after connecting the cnvss pin to vss and starting from reset. the function differs between the external bus mode a and the external bus mode b. ?external bus mode a _ ___ _ pin e/rde becomes the output pin for signal e . _ e is an enable signal and is l during the data/instruction code read or data write term. when the internal memory area is read or written, _ e can be fixed to h by setting the signal output disabe selection bit (bit 6 of the oscillation circuit control register 0) to 1. port p0 becomes an address output pin and loses its i/o port function. port p1 has two functions depending on the level of the byte pin. in both cases, the i/o port function is lost. when the byte pin level is l, port p1 functions as an address __ output pin while e is h and as an odd address data i/o pin while e is l. however, if an internal memory is read, external data is ignored _ while e is l. when the byte pin level h, port p1 functions as an address output pin. however, in the external bus mode b, banks 10 16 to ff 16 cannot be accessed. additionally, the evaluation chip mode cannot also be selected.
53 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer port p2 has two functions depending on the level of the byte pin. in both cases, the i/o port function is lost. when the byte pin level is ?? port p2 functions as an addr ess output pin while e is ??and as an even address data i/o pin while e is ?? however, if an internal memory is read, external dat a is ignored _ while e is ?? when the byte pin level is ?? port p2 functions as an addr ess _ output pin while e is ??and as an even and odd address data i/o pin _ while e is ?? however, if an internal memory is read, external da ta is _ ignored while e is ?? _ ___ ____ ports p3 0 , p3 1 , p3 2 , and p3 3 become r/ w , bhe , ale, and hlda output pin respectively and lose their i/o port functions. _ r/ w is a read/write signal which indicates a read when it is ? ?and a write when it is ?? ___ bhe is a byte high enable signal which indicates that an odd ad dress is accessed when it is ?? therefore, two bytes at even and odd addresses are accessed ___ simultaneously when address a 0 is ??and bhe is ?? ale is an address latch enable signal used to latch the addr ess signal from a multiplexed signal of address and data. the latch is transparent while ale is ??to let the address signal pass through and held while ale is ?? ____ hlda is a hold acknowledge signal and is used to notify external ly ____ when the microcomputer receives hold input and enters hold state. ____ ___ ports p4 0 and p4 1 become hold and rdy input pin, respectively, and lose their output pin function. ____ hold is a hold request signal. it is an input signal used to put the ____ microcomputer in hold state. hold input is accepted when the internal clock falls from ??level to ??level while the bus is not used. ports p0, p1, p2, p3 0 and p3 1 are floating while the microcomputer stays in hold state. these ports become floating after one c ycle of ____ internal clock later than hlda signal changes to ??level. at releasing hold state, these ports are released from floating state after ____ one cycle of internal clock later than hlda signal changes to ? level. ___ rdy is a ready signal. when this signal goes ?? the internal clock ___ stops at ?? rdy is used when a slow external memory is attached. port p4 2 becomes a normal i/o port when bit 7 of the processor mode register 0 is ??and becomes an output pin for clock 1 when ___ bit 7 is 1. the 1 output is independent of rdy and does not stop ___ even when internal clock stops because of l input to the rdy pin. ?external bus mode b _ ___ ___ pin e / rde becomes the output pin for rde . ___ rde is a read-enable signal and is ??during the data read ter m in ___ the read cycle. when the internal memory area is read, rde can be fixed to ??by setting the signal output disabe selection b it (bit 6 of the oscillation circuit control register) to ?? ports p0 6 and p0 7 become the output pins for addresses a 16 and ____ a 17 , respectively. similarly, port p0 5 becomes the output pin for rsmp , ___ ___ and ports p0 0 to p0 4 become the output pins for cs 0 to cs 4 , respectively. in this case, their functions as i/o ports are lost. ___ ___ cs 0 to cs 4 are the chip select signals and are ??when the address ____ shown in table 8 is accessed. rsmp is the ready-sampling signal ___ which is output for the rdy input described later when the external ____ memory area is accessed. by inputting logical and of rsmp and ___ ___ cs n (n = 0 to 4) to the rdy pin, read/write term for any address areas can be extended by 1 cycle of clock 1 . in addition, the read/write term can also be extended by 2 cycles of clock 1 if the above function and wait 0/1 function specified with the wait bit a re used together. port p1 has two functions depending on the level of the byte pin. in bose cases, the i/o port function is lost. when the byte pin level is l, port p1 functions as an addr ess (a 15 ___ ___ ___ to a 8 ) output pin while rde or wel , weh are h and as an odd ___ ___ ___ address data i/o pin while rde or wel , weh are l. however, if an ___ internal memory is read, external data is ignored while rde is l. when the byte pin level is h, port p1 functions as an addr ess output pin. port p2 has two functions depending on the level of the byte pin. in bose cases, the i/o port function is lost. when the byte pin level is l, port p2 functions as an addr ess (a 0 ___ ___ ___ to a 7 ) output pin while rde or wel , weh are h and as an even ___ ___ ___ address data i/o pin while rde or wel , weh are l. however, if an ___ internal memory is read, external data is ignored while rde is l. when the byte pin level is h, port p2 functions as an addr ess (a 0 ___ ___ ___ to a 7 ) output pin while rde or wel , weh are h and as an even and ___ ___ ___ odd address data i/o pin while rde or wel , weh are l. however, if ___ an internal memory is read, external data is ignored while rde is l. ___ ___ ____ ports p3 0 , p3 1 , p3 2 , and p3 3 become wel , weh , ale, and hlda output pins, respectively and lose their i/o port functions. ___ ___ wel , weh are the write-enable low signal and the write-enable high signal, respectively. these signals go l during the data w rite term of the write cycle, but their operations differ depending on the byte pin level. ___ in the case the byte pin level is l, wel is l when writing to ___ an even address, weh is l when writing to an odd address, and ___ ___ both wel and weh are l when writing to even and odd addresses. in the case the byte pin level is h, regardless of address , only ___ ___ ___ ___ wel is l, and weh retains h. wel and weh can also be fixed to ___ h when the internal memory is accessed, same as rde , by writing 1 to the signal output disable selection bit. ale is an address latch enable signal used to latch the addr ess signal from a multiplexed signal of address and data. the latch is transparent while ale is h to let the address signal pass through and held while ale is l. ____ hlda is a hold acknowledge signal and is used to notify external ly ____ when the microcomputer receives hold input and enters into hole state. ____ ___ ports p4 0 and p4 1 become hold and rdy input pin, respectively, and lose their output pin function. ____ hold is a hold request signal. it is an input signal used to put the ____ microcomputer in hold state. hold input is accepted when the internal clock falls from h level to l level while the bus is not used. _ ___ ports p0, p1, p2, p3 0 , p3 1 , and pin e / rde are floating while the microcomputer stays in hold state. these ports become floati ng after ____ one cycle of internal clock later than hlda signal changes to l level. at releasing hold state, these ports are released fro m floating ____ state after one cycle of internal clock later than hlda signal changes to h level. ___ rdy is a ready signal. if this signal goes l, the internal cl ock ___ stops at l. rdy is used when slow external memory is attached. port p4 2 becomes a normal i/o port when bit 7 of the processor
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 54 mode register 0 is 0 and becomes an output pin for clock 1 when ___ bit 7 is 1. the 1 output is independent of rdy and does not stop ___ even when internal clock stops because of l input to the rdy pin.
55 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer single-chip mode _ e _ enable signal e is output. l is output. _ ___ ___ ___ e, rde, wel, weh _ ___ ___ ___ e, rde, wel, weh are output when the internal/external memory area is accessed. l is output after wit/stp instruction is executed. * standby state selection bit (bit 0 of port function control register) must be set to 1. hor l is output. (output the content of p4 2 latch.) * port p4 2 direction register must be set to 1. (3) microprocessor mode [10] microprocessor mode is entered by connecting the cnvss pin to vcc and starting from reset. it can also be entered by programming the processor mode bits to 10 after connecting the cnvss pin to vss and starting from reset. this mode (for both the external bus mode a and the external bus mode b) is similar to the memory expansion mode except that internal rom is disabled and an external memory is required, and clock 1 from port p4 2 is always output independently of bit 7 of the processor mode register 0. as shown in table 7, 1 output can also be stopped with the signal output disable selection bit 1. in this case, write 1 to the port p4 2 direction register. (4) evaluation chip mode [11] evaluation chip mode can be selected at the external bus mode a only. evaluation chip mode is entered by applying voltage twice the v cc voltage to the cnv ss pin. this mode is normally used for evaluation tools. _ the functions of e , ports p0 and p3 are the same as those in memory expansion mode. _ port p1 functions as an address output pin while e is h and as data _ i/o pin of odd addresses while e is l regardless of the byte pin level. _ port p2 function as an address output pin while e is h and as data _ i/o pin of even addresses while e is l when the byte pin level is l. when the byte pin level is h or 2v cc , port p2 functions as an _ address output pin while e is h and as data i/o pin of even and odd _ addresses while e is l. port p4 and its data direction register which are located at address 0a 16 and 0c 16 are treated differently in evaluation chip mode. when these addresses are accessed, the data bus width is treated as 16 bits regardless of the byte pin level, and the access cycle is treated as internal memory regardless of the wait bit. when a voltage twice the v cc voltage is applied to the byte pin, the addresses corresponding to the internal rom area are also treated as 16-bit data bus. the functions of ports p4 0 and p4 1 are the same as in memory expansion mode. ports p4 2 to p4 6 become 1 , mx, qcl, vda, and vpa output pins ___ respectively. port p4 7 becomes the dbc input pin. 1 from port p4 2 is always output regardless of bit 7 of processor mode register 0. signal mx normally contains the contents of flag m, however, the contents of flag x is output when the cpu is using flag x. qcl is the queue buffer clear signal. it becomes h when the instruction queue buffer is cleared, for example, when a jump instruction is executed. vda is the valid data address signal. it becomes h while the cpu is reading data from data buffer or writing data to data buffer. it also becomes h when the first byte of the instruction (operation code) is read from the instruction queue buffer. vpa is the valid program address signal. it becomes h while the cpu is reading an instruction code from the instruction queue buffer. ___ dbc is the debug control signal and is used for debugging. table 9 shows the relationship between the cnvss pin input level and the processor modes. table 9. relationship between cnvss pin input levels and processor modes cnvss mode description single-chip mode upon starting after reset. each mode can be selected by changing the processor mode bits by software. microprocessor mode upon starting after reset. evaluation chip mode only. ? single-chip ? memory expansion ? microprocessor (? evaluation chip) ? microprocessor (? evaluation chip) ? evaluation chip vss vcc 2vcc table 7. function of signal output disable selection bit cm 6 (bit 6 of oscillation circuit control register 0) function cm 6 = 0 cm 6 = 1 processor mode pin after wit/stp instruction is executed, h is output. memory expansion mode, microprocessor mode _ ___ e, rde _ ___ ___ ___ e, rde, wel, weh are output only when the external memory area is accessed. note. functions shown in table 7 cannot be emulated in a debugger. for the oscillation circuit control register 0, refer to figure 64. for the port function control register, refer to figure 11. note. in the external bus mode b, the evaluation chip mode cannot be selected. clock 1 is output independent of 1 output selection bit. microprocessor mode 1
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 56 00 1000 16 to 00 7fff 16 02 0000 16 (note) 00 8000 16 to to 03 ffff 16 03 ffff 16 04 0000 16 04 0000 16 to to 07 ffff 16 07 ffff 16 08 0000 16 08 0000 16 to to 0b ffff 16 0b ffff 16 0c 0000 16 0c 0000 16 to to 0f ffff 16 0f ffff 16 ___ ___ table 8. relationship between access addresses and chip-select signals cs 0 to cs 4 (external bus mode b) access address memory expansion mode microprocessor mode chip-select signal area note. this applies when both bits 1 and 0 of the memory allocation control register is 0. refer to on the section rom area modification function. the latter half of bank 00 16 except for internal memory area and banks 01 16 to 03 16. banks 04 16 to 07 16 banks 08 16 to 0b 16 banks 0c 16 to 0f 16 the first half of bank 00 16 except for internal momory area ___ cs 0 ___ cs 1 ___ cs 2 ___ cs 3 ___ cs 4 (note)
57 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer oscillation circuit in the oscillation circuit, two kinds of clock circuits are built-in. one is the main-clock oscillation circuit which uses the x in and x out pins, and the other is the sub-clock (32 khz) oscillation circuit which uses the x cin and the x cout pins. either of these two oscillation circuits can output the system clock, and it can be selected. figure 62 shows the oscillation circuit example with a ceramic resonator or a quartz-crystal oscillator connected. the circuit constants such as capacitance depend on a resonator/oscillator, and these constants shall be set to the resonator/oscillator manufactures recommended value. figure 63 shows the example of the external clock input circuit. when inputting the main clock externally, the main-clock oscillation circuit stops operating and power dissipation could be conserved by setting the main clock external input selection bit (bit 1 of the oscillation circuit control register 1, refer to figure 64) to 1. note that this bit also has the function to select a return factor from stp state (refer to the section on the standby function.) additionally, write to the oscillation circuit control register 1 as the flow shown in figure 65. pins x cin and x cout of the sub-clock oscillation circuit are also used as i/o ports p7 7 and p7 6 , and these functions are selected with the port-x c selection bit described below. from the time during reset to the time after releasing reset, only the main-clock oscillation circuit operates and the main clock is selected as the system clock. furthermore, at this time, the sub-clock oscillation circuit stops and pins x cin and x cout become i/o ports (p7 7 , p7 6 ). when the port-x c selection bit (bit 4 of the oscillation circuit control register 0) is set to 1 in this condition, i/o ports p7 7 and p7 6 are switched to pins x cin and x cout , and then, oscillation starts in the sub-clock oscillation circuit. x in x out x cin p7 6 left open external oscillation circuit vcc vss vcc vss (p7 6 as i/o port) external oscillation circuit ? when inputting the main clock externally, set the main clock external input selection bit to 1. then, leave the x out pin open. ? when inputting the sub clock externally, set the sub-clock external input selection bit to 1. then, port p7 6 becomes an i/o port. fig. 63 external clock input circuit when inputting the sub clock externally, set the sub-clock external input selection bit (bit 2 of the oscillation circuit control register 1) to 1 before selecting pins x cin and x cout with the port-xc selection bit. when the sub-clock external input selection bit is set to 1, port p7 6 becomes an i/o port (or an analog input an 6 ). note that this bit also has the function to select a return factor from stp state (refer to the section on the standby function.) when the sub-clock output selection bit (bit 1 of the port function control register, refer to figure 11) is set to 1 under the condition of the port-xc selection bit = 1, the sub-clock sub is output from port p6 7 . accordingly, the sub-clock 32 khz can be supplied for external devices. rf rd c in c out x in x out x cin x cout rcf rcd c cin c cout (32 khz) in this case, sub-clock oscillation circuit is used. (port-xc selection bit is 1) rf rd c in c out x in x out p7 7 p7 6 (p7 7 , p7 6 as i/o port) in this case, sub-clock oscillation circuit is not used. ( port-xc selection bit is 0) fig. 62 oscillation circuit example with external resonator or quartz-crystal oscillator
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 58 clock generating circuit figures 64 and 66 show the bit configuration of the oscillation circuit control registers 0, 1 and the clock generating circuit diagram. the clock generating circuit consists of main- and sub-clock oscillation circuits, system clock switch circuit, clock dividing circuit, standby control circuit, and others. the oscillation circuit control registers are some of the control registers for the clock generating circuit. clocks , f 2 to f 512 , f c32 , and 1 are used in cpu and internal peripheral devices or are output from pins, and they are made of the main or sub clock, as shown in figure 66. the system clock and the clock f 2 can be switched to high-speed clocks or low-speed clocks shown in table 10. when using the sub clock, it is possible to select one of 3 types: the main clock divided by 2, the direct main clock (not divided) and the sub clock divided by 2 as the clock f 2 . when not using the sub clock, it is possible to select one of 4 types: the main clock divided by 2, divided by 8, divided by 16 and the direct main clock (not divided) as the clock f 2 . this function of clocks switch make it possible to adapt power control to the system operation. bits 0 to 4 of the oscillation circuit control register 0 and bit 0 of the oscillation circuit control register 1 control sub-clock oscillation start, system clock selection, stop/restart of main-clock oscillation, sub- clock drivability selection and the main clock division selection. the method of clocks switch is described bellow. when selecting the main clock as the system clock, the main clock division selection bit (bit 0 of the oscillation circuit control register 1) selects either the main clock divided by 2 or the direct main clock as the clock f 2 . when this bit is 1, the clock f 2 is the direct main clock which is not divided, so that a half external input frequency is enough to perform the same operation speed. consequently, power dissipation could be conserved (refer to figure 70.) the main clock division selection bit is valid regardless of either using the sub clock or not. figure 67 shows the system clock state transition when using the sub clock. from the time during reset to the time reset is released, only the main clock, which is selected as the system clock, oscillates. if the port-x c selection bit is set to 1 in this term, the sub-clock oscillation circuit starts oscillation. when the sub clock is not used, fix the port-x c selection bit to 0 (0 at reset) and use the p7 7 /an 7 x cin and p7 6 /an 6 /x cout pins as i/o ports p7 7 and p7 6 or analog inputs an 7 and an 6 , respectively. table 10. selection of system clock and clock f 2 0 0 0 0 1 1 1 1 main clock main clock main clock divided by 8 main clock divided by 8 main clock main clock sub clock sub clock clock f 2 main clock divided by 2 main clock main clock divided by 16 main clock divided by 8 main clock divided by 2 main clock sub clock divided by 2 sub clock divided by 2 port-xc selection bit (cm 4 ) system clock selection bit (cm 3 ) 0 0 1 1 0 0 1 1 main clock division selection bit (cc 0 ) 0 1 0 1 0 1 0 1 system clock sub clock not used used
59 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer oscillation circuit control register 0 x cout drivability selection bit 0 : low 1 : high main clock stop bit 0 : main-clock oscillation is available. 1 : main-clock oscillation is stopped. system clock selection bit port-x c selection bit = ??(sub clock is not used.) 0 : main clock is selected. 1 : main clock divided by 8 is selected. port-x c selection bit = ??(sub clock is used.) 0 : main clock is selected. 1 : sub clock is selected. port-xc selection bit 0 : ports p7 7 and p7 6 are selected. (sub clock is not used.) 1 : pins x cin and x cout are selected. (sub clock is used.) system clock stop bit at wait state 0 : clocks f 2 to f 512 are operating at wit state 1 : clocks f 2 to f 512 stop at wit state signal output disable selection bit (refer to table 7.) address 6c 16 note. write to the oscillation circuit control register 1 as the flow shown in figure 65. cm 6 cm 5 cm 4 cm 3 cm 2 cm 0 76543210 oscillation circuit control register 1 main clock division selection bit 0 : main clock is divided by 2. 1 : main clock is not divided by 2. main clock external input selection bit 0 : main-clock oscillation circuit is operating by itself. watchdog timer is used at returning from stp state. 1 : main-clock is input externally. watchdog timer is not used at returning from stp state. sub clock external input selection bit 0 : sub-clock oscillation circuit is operating by itself. port p7 6 functions as x cout pin. watchdog timer is used at returning from stp state. 1 : sub-clock is input externally. port p7 6 functions as i/o port. watchdog timer is not used ar returning from stp state. x : not used 0 : always ??(however, writing data ?5 16 ?shown in figure 65 is possible.) clock prescaler reset bit address 6f 16 cc 0 cc 1 cc 2 0 76543210 fig. 64 bit configuration of oscillation circuit control registers 0, 1 fig. 65 how to write data in oscillation circuit control register 1 writing data ?0 16 ?(ldm instruction) reset clock prescaler writing data ?5 16 ?(ldm instruction) writing data ?y 16 ?(ldm instruction) cc 2 to cc 0 selection bits ?how to reset clock prescaler ?how to write in cc 2 to cc 0 selection bits note. ??is the sum of bits to be set. for example, when setting bits 2 and 1 to ?? ??becomes ?? next instruction
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 60 fig. 66 block diagram of clock generating circuit (oscillation circuit control register 0 : address 6c 16 ) cm 2 : main clock stop bit cm 3 : system clock selection bit cm 4 : port-xc selection bit cm 5 : system clock stop bit at wait state (oscillation circuit control register 1:address 6f 16 ) cc 0 : main clock division selection bit cc 1 : main clock external input selection bit cc 2 : sub clock external input selection bit (port function control register : address 6d 16 ) pc 1 : sub-clock output selection bit/timer b2 clock source selection bit p7 6 /x cout p7 7 /x cin p6 7 /tb2 in / sub cm 4 pc 1 cm 4 cm 4 cc 2 x out x in main clock cm 4 system clock cc 0 cm 3 cm 3 cm 3 cm 2 cc 1 cm 4 cm 5 qs r stp instruction wit instruction p4 2 / 1 cm 3 f 512 f 64 wdc 12-bit watchdog timer watchdog timer frequency selection flag reset cc 1 cc 2 cm 3 cm 4 interrupt disable flag interrupt request stp instruction r q ss q r 1 0 1 1 1 1 1 1 1 1 f 2 f 8 f 16 f 32 0 0 0 0 1 0 1 0 0 0 0 0 sub clock (port latch) pc 1 cm 4 1/32 clock prescaler f c32 timer b 2 (clock timer) (in event counter mode) 1/2 1/4 1/2 1/2 1/2 1/8 internal clock 1/8
61 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer main clock : oscillating sub clock : stopped i/o ports p7 7 and p7 6 f 2 : main-clock side : main-clock side main clock : oscillating sub clock : stopped i/o ports p7 7 and p7 6 f 2 : main-clock side (note 2) : stopped main clock : stopped sub clock : stopped i/o ports p7 7 and p7 6 f 2 : stopped : stopped wit instruction interrupt stp instruction interrupt x c is selected (cm 4 = 1) main clock : oscillating sub clock : oscillating f 2 : main-clock side : main-clock side main clock : oscillating sub clock : oscillating f 2 : main-clock side (note 2) : stopped main clock : stopped sub clock : stopped f 2 : stopped : stopped wit instruction interrupt stp intrunction interrupt sub clock is selected as system clock (note 1) (cm 3 = 1) main clock : oscillating sub clock : oscillating f 2 : sub-clock side : sub-clock side main clock : oscillating sub clock : oscillating f 2 : sub-clock side (note 2) : stopped main clock : stopped sub clock : stopped f 2 : stopped : stopped wit instruction interrupt stp intrunction interrupt main clock oscillation stops (cm 2 = 1) main clock : stopped sub clock : oscillating f 2 : sub-clock side : sub-clock side main clock :stopped sub clock :oscillating f 2 : sub-clock side (note 2) : stopped wit instruction interrupt reset main clock is selected as system clock (note 1) (cm 3 = 0) main clock oscillation starts (cm 2 = 0) notes1. before selecting the main/sub clock of which oscillation already starts as the system clock, use software to fully stabilize the oscillation. 2. when the system clock stop bit at wait state (cm 5 ) is 1, f 2 stops at wait state. main clock : stopped sub clock : stopped f 2 : stopped : stopped stp instruction interrupt fig. 67 system clock state transition
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 62 figure 68 shows the system clock selection change example when using the sub clock. when the system clock selection bit is 1 after sub-clock oscillation starts, the sub clock is selected as the system clock. make sure to select the sub clock after the sub-clock oscillation is fully stabilized. when the main clock stop bit is set to 1 after the sub clock is selected, the main-clock oscillation/input stops. by stopping the main-clock oscillation, current consumption can be further restricted. when the main clock stop bit is cleared to 0 after the main-clock oscillation stops, the main-clock oscillation/input restarts. when the system clock selection bit is 0 after the main-clock oscillation restarts, the main clock is selected as the system clock again. make sure to select the main clock after the main-clock oscillation restarts and is fully stabilized. the x cout drivability selection bit is a bit to select the drivability of the sub-clock oscillation circuit and is set to 1 (high) after reset is released. make sure to clear the x cout drivability selection bit to 0 (low) after the sub-clock oscillation is fully stabilized. note that the port-x c selection bit cannot be cleared by software when it is once set to 1. the bit can be cleared only by reset. it is impossible to write 1 to the port-x c selection bit and the system clock selection bit at the same time. in addition, the contents of the main clock stop bit and the x cout drivability selection bit cannot be changed when the port-x c selection bit is 0. port-xc selection bit (cm 4 ) system colck selection bit (cm 3 ) main clock stop bit (cm 2 ) system clock main-clock oscillation sub-clock oscillation oscillation stabilizing time stop operating operating operating oscillation stabilizing time main clock sub clock main clock stopped fig. 68 system clock selection change example
63 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer when the port-x c selection bit is set to 1 to use sub-clock oscillation and timer b2 is set to be in the event count mode, clock f c32 which is the sub clock (32 khz) divided by 32 is selected as the count source of timer b2. by this selection, timer b2 can be used as the clock timer. for setting of timer b2 related registers, refer to the section on clock timer mode of timer b2. the clock prescaler in which the sub clock is divided by 32 is reset by writing 1, in dummy, into bit 7 (clock prescaler reset bit) of the oscillation circuit control register 1. when the main clock is selected, by this function, clock f c32 of clock timer b2 can be synchronized with software. figure 69 shows the operation timing for clock prescaler and clock timer b2. figure 70 shows the clock f 2 state transition when the port-xc selection bit is 0 and the sub clock is not used. fig. 70 clock f 2 state transition (when the sub clock is not used.) from the time during reset to the time reset is released, the main clock divided by 2 is being selected as the clock f 2 . when the system clock selection bit is set 1 in that condition, the main clock divided by 16 is selected as the clock f 2 and the clock frequency supplied for the cpu and internal peripheral devices is divided by 8 more. it makes current consumption restrict, although the operation speed slows. when the timer b2 clock source selection bit (bit 1 of the port function control register) is set to 1 and event counter mode is selected in timer b2 under the condition which the port-xc selection bit is 0; fc 32 , which is the main clock divided by 32, is connected as a timer bs count source. accordingly, timer b2 can be used as a clock timer which always operates with a regular clock source shown in figure 70. for details relating to register setting of timer b2, refer to the section clock timer on timer b. fig. 69 operation timing for clock prescaler and clock timer b2 cc 0 = 0 cc 0 = 1 cm 3 = 0 cm 3 = 1 f 2 = f(x in ) / 2 (note 1) f 2 = f(x in ) / 16 f 2 = f(x in ) / 2 (note 1) f 2 = f(x in ) (note 2) f 2 = f(x in ) / 8 cm 3 = 0 cc 0 = 0 cm 3 = 1 cc 0 = 1 reset notes 1. f 2 = f(x in ) / 2 expresses that the clock f 2 is the main clock divided by 2. 2. f 2 = f(x in ) expresses that the clock f 2 is the direct main clock, which is not divided. cc 0 = main clock division selection bit cm 3 = system clock selection bit cm 4 = port-xc selection bit ? in the case of not using sub clock (cm 4 = 0) timer b2 count start flag writing pulse of clock prescaler reset bit x cin timer b2 count value n (set value) n C 1 x cin 31(cycle) x cin 32 (cycle) this applies when the main clock is selected as the system clock (system clock selection bit (cm 3 ) = 0). note. period of fc 32 =x cin 31 (cycle) (only in this term) period of fc 32 =x cin 32 (cycle) (after this term) (note) clock source of clock timer(fc 32 )
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 64 standby function the wit and the stp instructions make the microcomputer standby state. table 11 shows the relationship between standby state and each blocks operation. when the wit instruction is executed with the system clock stop bit at wait state (bit 5 of the oscillation circuit control register 0) = 0, internal clock is stopped being at l, but the oscillation circuit, system clock, and divided clocks f 2 to f 512 are not stopped. because divided clocks f 2 to f 512 are not stopped, a part of internal peripheral devices which use these divided clocks can operate even at wait state. otherwise, when the wit instruction is executed with the system clock stop bit at wait state = 1, the oscillation circuit is not stopped, but the system clock, divided clocks, and internal clock are stopped. accordingly, in this case, all of the internal peripheral devices which use divided clocks f 2 to f 512 , including the watchdog timer, are stopped. when port-x c selection bit is 1 to operate the sub-clock oscillation circuit, however, clock timer b2 can operate because clock f c32 for the clock timer is not stopped. when internal peripheral devices are not used, later wait state (system clock stop bit at wait state = 1) is more effective to restrict the current consumption. make sure to set the system clock stop bit at wait state to 1 immediately before the wit instruction execution and clear the bit to 0 immediately after the wait state is terminated. the wait state is terminated when an interrupt request is accepted, and the internal clock operation is restarted. at this time, interrupt processing can immediately be executed because oscillation circuits operation is not stopped during the wait state. when the stp instruction is executed, the oscillation circuit is stopped with internal clock stopped at l. furthermore, fff 16 is automatically set into the watchdog timer, and the clock source of the watchdog timer is forced to connect with f 32 when the main clock is selected or f 8 when the sub clock is selected. this connection is cut off when the most significant bit of the watchdog timer is cleared to 0 or the microcomputer is reset, and the clock source is connected with the input depending on the content of the watchdog timer frequency selection flag. in the stop state, internal peripheral devices using divided clocks f 2 to f 512 are stopped. the stop state is terminated by system reset or interrupt request acceptance, and then oscillation is restarted. at this time, supply of system clock and divided clocks f 2 to f 512 is restarted. in that condition, when the main clock external input selection bit is 0 and the main clock is being selected as a system clock, or when the sub clock external input selection bit is 0 and the sub clock is being selected as a system clock, internal clock is stopped at l till the most significant bit of the watchdog timer decremented with divided clock f 32 or f 8 becomes 0. however, supply of internal clock is restarted immediately after the oscillation restarts by reset. accordingly, in this case, it is necessary to wait for the oscillation stabilized before making the reset input h. otherwise in that condition, when the main clock external input selection bit is 1 and the main clock is being selected as a system clock, or when the sub clock external input selection bit is 1 and the sub clock is being selected as a system clock, supply of internal clock is restarted from the seventh clock of clock f 2 after the oscillation restarts. by this function, the microcomputer can immediately return from the stop state when the clock supply input from the external is stabilized. even though the main clock or the sub clock is input externally, make sure to clear the main clock external input selection bit or the sub clock external input selection bit to 0 before executing the stp instruction if this external clock is unstable for a short time at a return from the stop state. operation enabled (watchdog timer is operating) operation disabled (watchdog timer is stopped) (clock timers operation is enabled) operation disabled (watchdog timer is stopped) table 11. relationship between standby state and each blocks operation operation at wit/stp state instruction oscillation circuit system clock f 2 C f 512 clock output 1 internal clock system clock stop bit at wait state stopped (l) stopped (l) stopped (l) operating stopped (l) stopped (l) operating stopped stopped operating stopped stopped 0 1 wit stp internal peripheral devices using f 2 C f 512 stopped (note) operating (note) operating note. when the main clock external input selection bit is 1, the main clock oscillation circuit stops. when the sub clock external input selection bit is 1, the sub-clock oscillation circuit stops. (in both cases, the external clock can be input.)
65 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer the wait/stop state is terminated by interrupt acceptance or reset. accordingly, it is necessary to prepare the state in which any interrupt can be accepted before the wit/stp instruction is executed. additionally, it is necessary to set the system clock stop bit at wait state before the wit instruction is executed. when the wit/stp instruction is executed in a bus access cycle, the _ ___ ___ ___ bus enters the non-access state ( e, rde, wel, weh are at h) because internal clock (or oscillation) is stopped after the read/ ___ ____ write in this cycle is finished. pins p0 0 /a 0 / cs 0 to p3 3 / hlda normally retain the state at which internal clock is stopped in the wait/stop state. however, only in the memory expansion mode and the microprocessor mode, arbitrary data which is set in the port p0 to p3 latches can be ___ ____ output from pins p0 0 /a 0 / cs 0 to p3 3 / hlda even at the wait/stop state when the following conditions are satisfied before the wit/stp instruction execution. ? the standby state selection bit (bit 0 of the port function control register) is set to 1. ? ff 16 is set into the port p0 to p3 direction registers. furthermore, when the standby state selection bit is set to 1 and bit 6 of the oscillation circuit control register 0 (signal output disable _ ___ selection bit) is set to 1, l level can be output from the e/rde pin at the wait/stop state. for the signal output disable selection bit, refer to table 7 on the processor mode section. note that the function of arbitrary data output cannot be emulated using a debugger.
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 66 rom area modification function the internal rom size and ram size of the M37736MHBXXXGP c a n be modified by the memory allocation control register?s bits 0,1 and 2 shown in figure 71. figure 73 shows the memory allocation in which the internal rom size and ram size are modified. make sure to write data in the memory allocation control reg ister as the flow shown in figure 72. this rom area modification function is valid in memory expan sion mode and single-chip mode. table 12 shows the relationship between the memory allocatio n selection bits and addresses corresponding to chip-select si gnals ___ ___ cs 0 and cs 1 in the memory expansion mode with the external bus mode b. when ordering a mask rom, mitsubishi electric corp. produces the mask rom using the data within 128 kbytes (addresses 000000 16 e 01ffff 16 ). it is regardless of the selected rom size (refer to mask rom order confirmation form.) therefore, program ff 16 to the addresses out of the selected rom area in the eprom w hich you tender when ordering a mask rom. address 01ffff 16 of this microcomputer corresponds to the lowest address of the eprom which you tender. 76543210 00 m l 2 ml 1 ml 0 memory allocation control register memory allocation selection bits rom size ram size 0 0 0 : 124 kbytes 3968 bytes 0 0 1 : 120 kbytes 3968 bytes 0 1 0 : 60 kbytes 2048 bytes 1 0 0 : 32 kbytes 2048 bytes 1 0 1 : 16 kbytes 2048 bytes 1 1 0 : 96 kbytes 3968 bytes 0 0 : always 00 (however, writing data 55 16 shown in figure 72 is possible.) address 63 16 note. write to the memory allocation control register as the flow shown in figure 72. writing data 55 16 (ldm instruction) writing data 0y 16 (ldm instruction) ml 2 , ml 1 , ml 0 selection bits next instruction how to write in memory allocation control register note. y is the sum of bits to be set. for example, when setting bit 1 to 1, y becomes 2. fig. 71 bit configuration of memory allocation control regi ster memory allocation selection bits internal rom area access addresses cs 0 cs 1 ml 2 ml 1 ml 0 0 0 0 1 1 1 0 0 1 0 0 1 0 1 0 0 1 0 001000 16 e 01ffff 16 002000 16 e 01ffff 16 001000 16 e 00ffff 16 008000 16 e 00ffff 16 00c000 16 e 00ffff 16 008000 16 e 01ffff 16 ?????? 001000 16 e 001fff 16 000880 16 e 000fff 16 000880 16 e 007fff 16 000880 16 e 007fff 16 001000 16 e 007fff 16 020000 16 e 03ffff 16 020000 16 e 03ffff 16 010000 16 e 03ffff 16 010000 16 e 03ffff 16 008000 16 e 00bfff 16 010000 16 e 03ffff 16 020000 16 e 03ffff 16 table 12 relationship between memory allocation selection b its and addresses corresponding to chip-select signals cs 0 and cs 1 in memory expansion mode (external bus mode b) fig. 72 how to write data in memory allocation control regi ster
67 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer internal ram 3968 bytes internal ram 3968 bytes internal ram 2048 bytes sfr sfr sfr (4 kbytes) (1.9 kbytes) internal rom 120 kbytes internal rom 124 kbytes internal rom 60 kbytes 000000 16 00007f 16 000080 16 000fff 16 000000 16 00007f 16 000080 16 000fff 16 002000 16 000000 16 00007f 16 000080 16 00087f 16 001000 16 001000 16 010000 16 01ffff 16 01ffff 16 ffffff 16 ffffff 16 ffffff 16 00ffff 16 010000 16 00ffff 16 010000 16 00ffff 16 (ml 2 , ml 1 , ml 0 ) = (0, 0, 0) (ml 2 , ml 1 , ml 0 ) = (0, 0, 1) (ml 2 , ml 1 , ml 0 ) = (0, 1, 0) : external memory area internal ram 2048 bytes internal ram 2048 bytes internal ram 3968 bytes sfr sfr sfr (45.9 kbytes) (28 kbytes) internal rom 16 kbytes internal rom 32 kbytes internal rom 96 kbytes 000000 16 00007f 16 000080 16 00087f 16 000000 16 00007f 16 000080 16 00087f 16 00c000 16 000000 16 00007f 16 000080 16 000fff 16 008000 16 008000 16 010000 16 ffffff 16 ffffff 16 ffffff 16 00ffff 16 010000 16 00ffff 16 010000 16 00ffff 16 (ml 2 , ml 1 , ml 0 ) = (1, 0, 0) (ml 2 , ml 1 , ml 0 ) = (1, 0, 1) (ml 2 , ml 1 , ml 0 ) = (1, 1, 0) (29.9 kbytes) 01ffff 16 note. in the external bus mode b, banks 10 16 to ff 16 cannot be accessed. fig. 73 memory allocation (modification of internal rom and ram area by memory allocation selection bits)
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 68 addressing modes the M37736MHBXXXGP has 28 powerful addressing modes. refer to the 7700 family software manual for the details. machine instruction list the M37736MHBXXXGP has 103 machine instructions. refer to the 7700 family software manual for the details. data required for mask rom ordering please send the following data for mask orders. (1) M37736MHBXXXGP mask rom order confirmation form (2) 100p6s mark specification form (3) rom data (eprom 3 sets)
69 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer symbol parameter conditions ratings unit vcc power source voltage C0.3 to +7 v avcc analog power source voltage C0.3 to +7 v v i _____ input voltage reset , cnvss, byte C0.3 to +12 v input voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3, p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7, p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 7 , v ref , x in, bsel output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3, p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, _ p9 0 C p9 7 , p10 0 C p10 7 , x out , e p d power dissipation ta = 25 c 300 mw t opr operating temperature C20 to +85 c t stg storage temperature C 40 to +150 c absolute maximum ratings limits min. typ. max. f(x in ) : operating 4.5 5.0 5.5 f(x in ) : stopped, f(x cin ) = 32.768 khz 2.7 5.5 avcc analog power source voltage vcc v vss power source voltage 0v avss analog power source voltage 0 v high-level input voltage p0 0 C p0 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , _____ p7 0 C p7 7 , p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 7 , x in , reset , cnvss, byte, bsel, x cin (note 3) high-level input voltage p1 0 C p1 7 , p2 0 C p2 7 (in single-chip mode) high-level input voltage p1 0 C p1 7 , p2 0 C p2 7 (in memory expansion mode and microprocessor mode) low-level input voltage p0 0 C p0 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , _____ p7 0 C p7 7 , p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 7 , x in , reset , cnvss, byte, bsel, x cin (note 3) low-level input voltage p1 0 C p1 7 , p2 0 C p2 7 (in single-chip mode) low-level input voltage p1 0 C p1 7 , p2 0 C p2 7 (in memory expansion mode and microprocessor mode) high-level peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 0 C p10 7 high-level average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 0 C p10 7 low-level peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 3 , p5 4 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 4 C p10 7 low-level peak output current p4 4 C p4 7 , p10 0 C p10 3 low-level average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 3 , p5 4 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 4 C p10 7 i ol(avg) low-level average output current p4 4 C p4 7 , p10 0 C p10 3 15 ma f(x in ) main-clock oscillation frequency (note 4) 25 mhz f(x cin) sub-clock oscillation frequency 32.768 50 khz unit symbol parameter recommended operating conditions (vcc = 5 v 10%, ta = C20 to +85 c, unless otherwise noted) v vcc power source voltage v ih v ih v ih v il v il v il i oh(peak) i oh(avg) i ol(peak) i ol(peak) i ol(avg) notes 1. average output current is the average value of a 100 ms interval. 2. the sum of i ol(peak) for ports p0, p1, p2, p3, p8, and p9 must be 80 ma or less, the sum of i oh(peak) for ports p0, p1, p2, p3, p8, and p9 must be 80 ma or less, the sum of i ol(peak) for ports p4, p5, p6, p7, and p10 must be 100 ma or less, and the sum of i oh(peak) for ports p4, p5, p6, p7, and p10 must be 80 ma or less. 3. limits v ih and v il for x cin are applied when the sub clock external input selection bit = 1. 4. the maximum value of f(x in ) = 12.5 mhz when the main clock division selection bit = 1. 0.8 vcc 0.8 vcc 0.5 vcc 0 0 0 vcc vcc vcc 0.2vcc 0.2vcc 0.16vcc C10 C5 10 20 5 v v v v v v ma ma ma ma ma v i v o C0.3 to vcc + 0.3 v C0.3 to vcc + 0.3 v
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 70 unit electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) symbol parameter test conditions v v oh high-level output voltage _ e v oh high-level output voltage p3 0 C p3 2 v ol _ low-level output voltage e v ol low-level output voltage p3 0 C p3 2 v oh v ol i il low-level input current p10 4 C p10 7 , p6 2 C p6 4 i il i ih v oh v ol i oh = C400 m a 4.7 v v v i ol = 2 ma 0.45 v v i ol = 10 ma 2v v i = 0 v v i = 5 v m a ma m a m a 5 C5 C1.0 C5 C0.5 C0.25 limits min. typ. max. high-level output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 0 C p10 7 high-level output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 3 i oh = C10 ma 3.1 i ch = C400 m a 4.8 i oh = C10 ma 3.4 i oh = C400 m a 4.8 low-level output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 3 , p4 0 C p4 3 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 5 , p8 0 C p8 7, p9 0 C p9 7 , p10 4 C p10 7 v ol low-level output voltage p4 4 C p4 7 , p10 0 C p10 3 i ol = 20 ma 2 v low-level output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 3 i ol = 10 ma 1.9 i ol = 2 ma 0.43 i ol = 10 ma 1.6 i ol = 2 ma 0.4 hysteresis ____ ___ hold , rdy , ta0 in C ta4 in , tb0 in C tb2 in , v t+ C v tC ___ ___ ____ ___ ___ ___ int 0 C int 2 , ad trg , cts 0 , cts 1 , cts 2 , clk 0 , 0.4 1 v __ __ clk 1 , clk 2 , ki 0 C ki 3 v t+ C v tC _____ hysteresis reset 0.2 0.5 v v t+ C v tC hysteresis x in 0.1 0.4 v v t+ C v tC hysteresis x cin (when external clock is input) 0.1 0.4 v high-level input current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , _____ p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 7 , x in , reset , cnvss, byte, bsel low-level input current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 , p6 1 , p6 5 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 3 , _____ x in, reset , cnvss, byte, bsel v i = 0 v, without a pull-up transistor v i = 0 v, with a pull-up transistor v ram ram hold voltage when clock is stopped. 2 i oh = C10 ma 3 v v
71 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer v cc = 5 v, f(x in ) = 25 mhz (square waveform), f(f 2 ) = 12.5 mhz, f(x cin ) = 32.768 khz, in operating (note 1) v cc = 5 v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 1.5625 mhz), f(x cin ) = stopped, in operating (note 1) v cc = 5v, f(x in ) = 25 mhz (square waveform), f(x cin ) = 32.768 khz, when a wit instruction is executed (note 2) v cc = 5 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, in operating (note 3) v cc = 5 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, when a wit instruction is executed (note 4) ta = 25 c, when clock is stopped ta = 85 c, when clock is stopped electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to 85 c, unless otherwise noted) max. limits typ. unit min. test conditions symbol parameter 9.5 1.3 10 50 5 20 2.6 19 100 10 1 ma ma m a m a m a m a m a power source current i cc in single-chip mode, output pins are open, and other pins are v ss . notes 1. this applies when the main clock external input selection bit = 1, the main clock division selection bit = 0, and the signal output stop bit = 1. 2. this applies when the main clock external input selection bit = 1 and the system clock stop bit at wait state = 1. 3. this applies when cpu and the clock timer are operating with the sub clock (32.768 khz) selected as the system clock. 4. this applies when the x cout drivability selection bit = 0 and the system clock stop bit at wait state = 1. 20 limits min. typ. max. resolution v ref = v cc 10 bits absolute accuracy v ref = v cc 3 lsb r ladder ladder resistance v ref = v cc 10 25 k w t conv conversion time 9.44 m s v ref reference voltage 2 v cc v v ia analog input voltage 0 v ref v symbol parameter test conditions unit aCd converter characteristics (v cc = av cc = 5 v, v ss = av ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note), unless otherwise noted) note. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz.
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 72 limits min. max. t su(dCe) data input setup time (external bus mode a) 32 ns t su(dCrde) data input setup time (external bus mode b) 32 ns t su(rdyC 1) ___ rdy input setup time 55 ns t su(holdC 1) ____ hold input setup time 55 ns t h(eCd) data input hold time (external bus mode a) 0 ns t h(rdeCd) data input hold time (external bus mode b) 0 ns t h( 1Crdy) ___ rdy input hold time 0ns t h( 1Chold) ____ hold input hold time 0ns limits min. max. t su(p0dCe) port p0 input setup time 60 ns t su(p1dCe) port p1 input setup time 60 ns t su(p2d-e) port p2 input setup time 60 ns t su(p3dCe) port p3 input setup time 60 ns t su(p4dCe) port p4 input setup time 60 ns t su(p5dCe) port p5 input setup time 60 ns t su(p6dCe) port p6 input setup time 60 ns t su(p7dCe) port p7 input setup time 60 ns t su(p8dCe) port p8 input setup time 60 ns t su(p10dCe) port p10 input setup time 60 ns t h(eCp0d) port p0 input hold time 0ns t h(eCp1d) port p1 input hold time 0ns t h(eCp2d) port p2 input hold time 0ns t h(eCp3d) port p3 input hold time 0ns t h(eCp4d) port p4 input hold time 0ns t h(eCp5d) port p5 input hold time 0ns t h(eCp6d) port p6 input hold time 0ns t h(eCp7d) port p7 input hold time 0ns t h(eCp8d) port p8 input hold time 0ns t h(eCp10d) port p10 input hold time 0ns limits min. max. t c external clock input cycle time (note 3) 40 ns t w(h) external clock input high-level pulse width (note 4) 15 ns t w(l) external clock input low-level pulse width (note 4) 15 ns t r external clock rise time 8ns t f external clock fall time 8ns timing requirements (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted (note)) notes 1. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2. input signals rise/fall time must be 100 ns or less, unless otherwise noted. external clock input unit symbol parameter unit symbol parameter single-chip mode notes 3. when the main clock division selection bit = 1, the minimum value of tc = 80 ns. 4. when the main clock division selection bit = 1, values of tw (h) / tc and tw (l) / tc must be set to values from 0.45 through 0.55. unit symbol parameter memory expansion mode and microprocessor mode
73 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer limits min. max. t c(ta) tai in input cycle time 80 ns t w(tah) tai in input high-level pulse width 40 ns t w(tal) tai in input low-level pulse width 40 ns unit symbol parameter timer a input (count input in event counter mode) limits min. max. t c(ta) tai in input cycle time (note) 320 ns t w(tah) tai in input high-level pulse width (note) 160 ns t w(tal) tai in input low-level pulse width (note) 160 ns unit symbol parameter timer a input (gating input in timer mode) limits min. max. t c(ta) tai in input cycle time (note) 320 ns t w(tah) tai in input high-level pulse width 80 ns t w(tal) tai in input low-level pulse width 80 ns unit symbol parameter timer a input (external trigger input in one-shot pulse mode) limits min. max. t w(tah) tai in input high-level pulse width 80 ns t w(tal) tai in input low-level pulse width 80 ns unit symbol parameter timer a input (external trigger input in pulse width modulation mode) limits min. max. t c(up) tai out input cycle time 2000 ns t w(uph) tai out input high-level pulse width 1000 ns t w(upl) tai out input low-level pulse width 1000 ns t su(upCt in ) tai out input setup time 400 ns t h(t in Cup) tai out input hold time 400 ns unit symbol parameter timer a input (up-down input in event counter mode) unit symbol parameter timer a input (two-phase pulse input in event counter mode) limits min. max. t c(ta) taj input cycle time 800 ns t su(taj in Ctaj out ) taj in input setup time 200 ns t su(taj out Ctaj in ) taj out input setup time 200 ns note. limits change depending on f(x in ). refer to data formulas on page 75. note. limits change depending on f(x in ). refer to data formulas on page 75.
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 74 limits min. max. t c(ad) ____ ad trg input cycle time (minimum allowable trigger) 1000 ns t w(adl) ad trg input low-level pulse width 125 ns limits min. max. t c(ck) clk i input cycle time 200 ns t w(ckh) clk i input high-level pulse width 100 ns t w(ckl) clk i input low-level pulse width 100 ns t d(cCq) t x d i output delay time 80 ns t h(cCq) t x d i hold time 0ns t su(dCc) r x d i input setup time 30 ns t h(cCd) r x d i input hold time 90 ns limits min. max. t c(tb) tbi in input cycle time (one edge count) 80 ns t w(tbh) tbi in input high-level pulse width (one edge count) 40 ns t w(tbl) tbi in input low-level pulse width (one edge count) 40 ns t c(tb) tbi in input cycle time (both edges count) 160 ns t w(tbh) tbi in input high-level pulse width (both edges count) 80 ns t w(tbl) tbi in input low-level pulse width (both edges count) 80 ns unit symbol parameter timer b input (count input in event counter mode) limits min. max. t c(tb) tbi in input cycle time (note) 320 ns t w(tbh) tbi in input high-level pulse width (note) 160 ns t w(tbl) tbi in input low-level pulse width (note) 160 ns unit symbol parameter timer b input (pulse period measurement mode) limits min. max. t c(tb) tbi in input cycle time (note) 320 ns t w(tbh) tbi in input high-level pulse width (note) 160 ns t w(tbl) tbi in input low-level pulse width (note) 160 ns unit symbol parameter timer b input (pulse width measurement mode) limits min. max. t c(ad) ____ ad trg input cycle time (minimum allowable trigger) 1000 ns t w(adl) ____ ad trg input low-level pulse width 125 ns unit symbol parameter a-d trigger input unit symbol parameter serial i/o limits min. max. t w(inh) ___ int i input high-level pulse width 250 ns t w(inl) ___ int i input low-level pulse width 250 ns t w(kil) __ ki i input low-level pulse width 250 ns unit symbol parameter limits min. max. t c(ck) clk i input cycle time 200 ns t w(ckh) clk i input high-level pulse width 100 ns t w(ckl) clk i input low-level pulse width 100 ns t d(cCq) t x d i output delay time 80 ns t h(cCq) t x d i hold time 0ns t su(dCc) r x d i input setup time 30 ns t h(cCd) r x d i input hold time 90 ns limits min. max. t c(tb) tbi in input cycle time (note) 320 ns t w(tbh) tbi in input high-level pulse width (note) 160 ns t w(tbl) tbi in input low-level pulse width (note) 160 ns unit symbol parameter timer b input (pulse width measurement mode) unit symbol parameter a-d trigger input unit symbol parameter serial i/o unit symbol parameter note. limits change depending on f(x in ). refer to data formulas on page 75. note. limits change depending on f(x in ). refer to data formulas on page 75. ______ ___ external interrupt int i input, key input interrupt ki i input
75 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer data formulas timer a input (gating input in timer mode) limits min. max. symbol parameter unit t c(ta) tai in input cycle time t w(tah) tai in input high-level pulse width t w ( tal ) tai in input low-level pulse width ns ns ns 8 5 10 9 2 f(f 2 ) timer a input (external trigger input in one-shot pulse mode) limits min. max. symbol parameter unit t c(ta) tai in input cycle time ns timer b input (in pulse period measurement mode or pulse width measurement mode) limits min. max. symbol parameter unit ns ns ns t c(tb) tbi in input cycle time t w(tbh) tbi in input high-level pulse width t w(tbl) tbi in input low-level pulse width 8 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) 8 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) note. f(f 2 ) represents the clock f 2 frequency. for the relation to the main clock and sub clock, refer to table 10.
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 76 limits min. max. t d(eCp0q) port p0 data output delay time 80 ns t d(eCp1q) port p1 data output delay time 80 ns t d(eCp2q) port p2 data output delay time 80 ns t d(eCp3q) port p3 data output delay time 80 ns t d(eCp4q) port p4 data output delay time 80 ns t d(eCp5q) port p5 data output delay time 80 ns t d(eCp6q) port p6 data output delay time 80 ns t d(eCp7q) port p7 data output delay time 80 ns t d(eCp8q) port p8 data output delay time 80 ns t d(eCp9q) port p9 data output delay time 80 ns t d(eCp10q) port p10 data output delay time 80 ns unit symbol parameter test conditions switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85c, f(x in ) = 25 mhz (note), unless otherwise noted) note. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 9 p10 1 e 50 pf fig. 74 measuring circuit for ports p0 C p10 and 1 fig. 74
77 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer [external bus mode a] memory expansion mode and microprocessor mode (v cc = 5 v 10%, v ss = 0 v, ta = 25 c, f(x in ) = 25 mhz (note 1), unless otherwise noted) symbol parameter t d(eCdq) t h(eCdq) address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time limits wait mode min. max. test conditions unit 45 5 12 87 12 75 18 22 57 5 45 9 15 4 10 18 50 130 20 12 87 12 87 18 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t d(anCe) t d(aCe) t d(aleCe) t h(eCan) t w(ale) t su(aCale) t h(aleCa) t w(el) data output delay time data hold delay time _ e pulse width floating start delay time floating release delay time ___ bhe output delay time _ r/ w output delay time ___ bhe hold time _ r/ w hold time no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 fig. 74 (note 2) 1 output delay time t pxz(eCdz) t pzx(eCdz) t d(bheCe) t d(r/wCe) t h(eCbhe) t h(eCr/w) t d(eC 1 ) t d( 1 Chlda) ____ hlda output delay time 0 18 50 notes 1. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2. no wait : wait bit = 1. wait 1 : the external memory area is accessed with wait bit = 0 and wait selection bit = 1. wait 0 : the external memory area is accessed with wait bit = 0 and wait selection bit = 0.
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 78 [external bus mode a] memory expansion mode and microprocessor mode bus timing data formulas (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (max., note), unless otherwise noted) address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time data output delay time data hold time _ e pulse width floating start delay time floating release delay time no wait wait 1 wait 0 45 5 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) ns ns ns ns ns ns ns ns ns ns no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 1 5 10 9 2 f(f 2 ) ns ns ns ns ns ns 9 4 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) ns ns 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) C 28 C 33 C 28 C 45 C 22 C 18 C 23 C 35 C 35 C 25 C 30 C 22 C 30 C 30 C 20 C 28 C 33 C 28 C 33 C 22 C 22 unit symbol parameter limits wait mode min. max. t d(anCe) t d(aCe) t h(eCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCe) t d(eCdq) t h(eCdq) t w(el) t pxz(eCdz) t pzx(eCdz) no wait wait 1 wait 0 ___ bhe output delay time _ r/ w output delay time t d(bheCe) t d(r/wCe) t h(eCbhe) t h(eCr/w) t d(eC 1) 1 output delay time _ r/ w hold time ___ bhe hold time 0 18 ns ns ns ns ns ns ns ns notes 1. this applies when the main-clock division selection bit = 0. 2. f(f 2 ) represents the clock f 2 frequency. for the relation to the main clock and sub clock, refer to table 10.
79 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer [external bus mode b] memory expansion mode and microprocessor mode (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1), unless otherwise noted) symbol parameter chip-select output delay time chip-select hold time address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time data output delay time data hold delay time ___ ___ wel / weh pulse width floating start delay time floating release delay time ___ rde pulse width ____ rsmp output delay time ____ rsmp hold time 1 output delay time ____ hlda output delay time limits wait mode min. max. test conditions t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) t d(anCwe) t d(anCrde) t d(aCwe) t d(aCrde) t h(weCan) t h(rdeCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCwe) t d(aleCrde) t d(weCdq) t h(weCdq) t w(we) t pxz(rdeCdz) t pzx(rdeCdz) t w(rde) t d(rsmpCwe) t d(rsmpCrde) t h( 1 Crsmp) t d(weC 1 ) t d(rdeC 1 ) t d( 1 Chlda) notes 1. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2. no wait : wait bit = 1. wait 1 : the external memory area is accessed with wait bit = 0 and wait selection bit = 1. wait 0 : the external memory area is accessed with wait bit = 0 and wait selection bit = 0. unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 45 5 18 50 12 87 4 12 87 12 75 18 22 57 5 45 9 15 4 10 18 50 130 20 48 128 10 0 0 fig. 73 (note 2) no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 80 [external bus mode b] memory expansion mode and microprocessor mode bus timing data formulas (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (max., note1), unless otherwise noted) 45 5 18 limits wait mode min. max. symbol parameter unit 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) ns ns no wait wait 1 wait 0 t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) t d(anCwe) t d(anCrde) t d(aCwe) t d(aCrde) t h(weCan) t h(rdeCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCwe) t d(aleCrde) t d(weCdq) t h(weCdq) t w(we) t pxz(rdeCdz) t pzx(rdeCdz) t w(rde) t d(rsmpCwe) t d(rsmpCrde) t h( 1 Crsmp) t d(weC 1 ) t d(rdeC 1 ) ns 4 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) ns ns ns ns ns ns ns ns ns ns no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 1 5 10 9 2 f(f 2 ) ns ns ns ns ns ns 9 4 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) ns ns 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) ns ns ns ns ns ns 0 0 chip-select output delay time chip-select hold time address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time data output delay time data hold time ___ ___ wel / weh pulse width floating start delay time floating release delay time ___ rde pulse width ____ rsmp output delay time ____ rsmp hold time 1 output delay time C 28 C 33 C 28 C 45 C 22 C 18 C 23 C 35 C 35 C 25 C 30 C 22 C 30 C 30 C 20 C 32 C 32 C 30 C 28 C 33 notes 1. this applies when the main-clock division selection bit = 0. 2. f(f 2 ) represents the clock f 2 frequency. for the relation to the main clock and sub clock, refer to table 10.
81 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer timing diagram t w(h) t d(e?iq) t d(e?2q) t d(e?3q) t d(e?4q) t d(e?5q) t d(e?6q) t d(e?7q) t d(e?8q) port pi output (i = 0 ?10) port pi input (i = 0 ?8, 10) port p1 output port p1 input port p2 output port p2 input port p3 output port p3 input e x in port p4 output port p4 input port p5 output port p5 input port p6 output port p6 input port p7 output port p7 input port p8 output port p8 input single-chip mode t su(pid?) t h(e?id) t d(e?1q) t r t f t w(l) t c t su(p1d?) t h(e?1d) t su(p2d?) t h(e?2d) t su(p3d?) t h(e?3d) t su(p4d?) t h(e?4d) t su(p5d?) t h(e?5d) t su(p6d?) t h(e?6d) t su(p7d?) t h(e?7d) t su(p8d?) t h(e?8d)
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 82 tai in input tai out input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in ?p) t su(up? in ) tai out input (up-down input) tai in input (when count by falling) tai in input (when count by rising) in event count mode taj in input taj out input t c(ta) t su(taj in ?aj out ) t su(taj in ?aj out ) t su(taj out ?aj in ) t su(taj out ?aj in ) in event counter mode (when two-phase pulse input is selected) t c(tb) t w(tbh) t w(tbl) tbi in input
83 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(knl) t d(c?) t su(d?) t h(c?) t w(inh) ad trg input clk i txd i rxd i inti input kli input t h(c?)
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 84 memory expansion mode and microprocessor mode (when wait bit = 1) ( when wait bit = 0) (when wait bit = 1 or 0 in common) test conditions ? v cc = 5 v 10% ? input timing voltage : v il = 1.0 v, v ih = 4.0 v ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v 1 rdy input 1 e or rde, wel, weh rdy input 1 hold input hlda output t su(rdyC 1 ) t h( 1 Crdy) t su(rdyC 1 ) t h( 1 Crdy) t su(holdC 1 ) t d( 1 Chlda) t h( 1 Chold) t d( 1 Chlda) e or rde, wel, weh
85 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 1 t d(e- 1) t d(an-e) t w(ale) t d(ale-e) t su(a-ale) t d(a-e) t d(e-dq) t h(ale-a) t d(bhe-e) t h(e-bhe) t d(r/w-e) t h(e-r/w) t h(e-dq) t pxz(e-dz) t su(d-e) t h(e-d) t pzx(e-dz) t h(e-an) t d(e- 1) t w(el) t w(h) e an ale am/dm dm in bhe r/ w address address address data data address address address t f t r t c t w(l) test conditions v cc = 5 v 10% output timing voltage : v ol = 0.8 v, v oh = 2.0 v data input dm in : v il = 0.8 v, v ih = 2.5 v x in [external bus mode a] memory expansion mode and microprocessor mode (no wait : when wait bit = 1) ? ? ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 86 t w(ale) t c address t w(l) t w(h) t f t r address address t d(eC 1 ) t d(anCe) t d(aleCe) t su(aCale) t h(aleCa) t d(aCe) t d(eCdq) t h(eCd) t pzx(eCdz) t h(eCbhe) t su(dCe) test conditions ? vcc = 5 v 10% ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v data address data t d(eC 1 ) address t pxz(eCdz) t w(el) t h(eCan) t h(eCdq) t h(eCr/w) t d(r/wCe) t d(bheCe) x in e an ale am/dm dm in bhe r /w 1 [external bus mode a] memory expansion mode and microprocessor mode (wait 1 : the external area is accessed when wait bit = 0 and wait selection = 1.)
87 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer [external bus mode a] t h(aleCa) t d(aleCe) t d(eCdq) t w(l) t w(h) t f t c t r memory expansion mode and microprocessor mode (wait 0 : the external memory area is accessed when wait bit = 0 and wait selection bit = 0.) x in 1 address address address address data an ale am/dm dm in r /w t d(anCe) t w(ale) t su(aCale) t h(eCdq) t d(aCe) t pxz(eCdz) t pzx(eCdz) t h(eCd) t su(dCe) address data address test conditions ? vcc = 5 v 10% ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v t d(eC 1 ) t d(eC 1 ) t d(r/wCe) t h(eCr/w) t w(el) t h(eCan) t d(bheCe) t h(eCbhe) e bhe
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 88 [external bus mode b] memory expansion mode and microprocessor mode (no wait : when wait bit = 1) t w(we) t h(weCdq) t w(l) t w(h) t f t r t c x in 1 cs 0 C cs 4 an ale am/dm t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) address t d(anCwe) t d(anCrde) t h(rdeCan) t w(ale) t d(aleCwe) address address t su(aCale) t h(aleCa) t d(aCwe) t d(aCrde) t d(aleCrde) t pxz(rdeCdz) t pzx(rdeCdz) address data address address wel, weh t h(weCan) t d(weCdq) dm in rde rsmp test conditions ? vcc = 5 v 10% ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v t su(dCrde) t h(rdeCd) t w(rde) t d(rsmpCwe) t h( 1 Crsmp) t d(rsmpCrde) data t d(rdeC 1 ) t d(weC 1 ) t d(weC 1 ) t d(rdeC 1 )
89 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer [external bus mode b] memory expansion mode and microprocessor mode (wait 1 : the external area is accessed when wait bit = 0 and wait selection bit = 1.) t c t w(l) t w(h) t f t r t w(ale) t d(anCwe) am/dm address t d(csCrde) t w(rde) t d(rde- 1 ) x in 1 address address cs 0 C cs 4 an ale wel, weh dm in rde rsmp t d(weC 1 ) t d(rdeC 1 ) t d(csCwe) t d(aleCwe) t h(rdeCan) t su(aCale) t h(aleCa) t d(aCwe) t d(weCdq) t w(we) t d(aCrde) t pzx(rdeCdz) t h(rdeCcs) t h(rdeCd) t su(dCrde) t d(rsmpCwe) t h( 1 Crsmp) t d(rsmpCrde) test conditions ? vcc = 5 v 10% ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v data address t h(weCcs) data t d(weC 1 ) t h(we-an) t d(aleCrde) t d(anCrde) t h(weCdq) address t pxz(rdeCdz)
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer 90 [external bus mode b] memory expansion mode and microprocessor mode (wait 0 : the external memory area is accessed when wait bit = 0 and wait selection bit = 0.) t c t r t h(aleCa) t d(aleCwe) t d(weCdq) t w(l) t w(h) t f x in 1 address address address address data cs 0 C cs 4 an ale am/dm wel , weh dm in rde rsmp t d(csCwe) t h(weCcs) t d(csCrde) t d(anCwe) t w(ale) t h(weCan) t d(anCrde) t h(rdeCan) t su(aCale) t h(weCdq) t d(aleCrde) t d(aCwe) t w(we) t d(aCrde) t pxz(rdeCdz) t pzx(rdeCdz) t h(rdeCcs) t h(rdeCd) t su(dCrde) t w(rde) t d(rsmpCwe) t h( 1 Crsmp) t d(rsmpCrde) address data address test conditions ? vcc = 5 v 10% ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v t d(weC 1 ) t d(rdeC 1 ) t d(rdeC 1 ) t d(weC 1 )
91 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer package outline
? 1996 mitsubishi electric corp. h-lf457-a ki-9611 printed in japan (rod) new publication, effective nov. 1996. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. mitsubishi microcomputers M37736MHBXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change.
rev. rev. no. date 1.00 first edition 970507 2.00 the following are revised: 980731 revision description list M37736MHBXXXGP datasheet (1) revision description page p4 p10 0 C p10 7 p5 right column line 7 p5 fig. 1 p9 right column line 12 p66 left column line 2 p66 fig.71 p67 fig. 73 p68 right column line 2 previous version additionally, the internal rom area can be modi- fied by software. notes 1. internal rom area can be modified. (re- fer to the section on rom area modifica- tion function.) the cpu operates on an internal clock f s fre- quency which is obtained by dividing the external clock frequency f(x in ) by two. the internal rom size and its address area of the M37736MHBXXXGP can be modified by the memory allocation control registers bits 0,1 and 2 shown in figure 71. figure 73 shows the memory allocation in which the internal rom size and its address area are modified. memory allocation selection bits rom size (rom area) 0 0 0 : 124 kbytes (addresses 001000 16 C 01ffff 16 ) 0 0 1 : 120 kbytes (addresses 002000 16 C 01ffff 16 ) 1 1 0 : 96 kbytes (addresses 008000 16 C 01ffff 16 ) 1 1 1 : 32 kbytes (addresses 008000 16 C 00ffff 16 ) refer to page (2). the M37736MHBXXXGP has 28 powerful addressing modes. refer to the single-chip 16- bit microcomputers data book for the details of each addressing mode. machine instruction list the M37736MHBXXXGP has 103 machine instructions. refer to the single-chip 16-bit microcomputers data book for details. revised version additionally, the internal rom and ram area can be modified by software. notes 1. internal rom and ram area can be modified. (refer to the section on rom area modification function.) the cpu operates on an internal clock f s frequency. the internal rom size and ram size of the M37736MHBXXXGP can be modified by the memory allocation control registers bits 0,1 and 2 shown in figure 71. figure 73 shows the memory allocation in which the internal rom size and ram size are modified. memory allocation selection bits rom size ram size 0 0 0 : 124 kbytes 3968 bytes 0 0 1 : 120 kbytes 3968 bytes 0 1 0 : 60 kbytes 2048 bytes 1 0 0 : 32 kbytes 2048 bytes 1 0 1 : 16 kbytes 2048 bytes 1 1 0 : 96 kbytes 3968 bytes refer to page (3). the M37736MHBXXXGP has 28 powerful addressing modes. refer to the 7700 family software manual for the details. machine instruction list the M37736MHBXXXGP has 103 machine instructions. refer to the 7700 family software manual for the details. previous version p10 0 ?p10 7 output port p10 i/o in addition to having the same functions as port p0 in the single-chip mode, p10 4 ?p10 7 also evl0, evl1 function as input pins for key input interrupt input (ki 0 ?ki 3 ). output these pins should be left open. revised version p10 0 ?p10 7 i/o port p10 i/o in addition to having the same functions as port p0 in the single-chip mode, p10 4 ?p10 7 also function as input pins for key input interrupt input (ki 0 ?ki 3 ). evl0, evl1 output these pins should be left open.
(2) revision description list M37736MHBXXXGP datasheet fig. 73 memory allocation (modification of internal rom area by memory allocation selection bit) internal ram 3968 bytes internal ram 3968 bytes internal ram 3968 bytes internal ram 3968 bytes sfr sfr sfr sfr (4 kbytes) (28 kbytes) (28 kbytes) internal rom 56 kbytes internal rom 60 kbytes internal rom 64 kbytes internal rom 64 kbytes internal rom 64 kbytes internal rom 32 kbytes internal rom 32 kbytes 000000 16 00007f 16 000080 16 000fff 16 000000 16 00007f 16 000080 16 000fff 16 002000 16 000000 16 00007f 16 000080 16 000fff 16 000000 16 00007f 16 000080 16 000fff 16 008000 16 008000 16 001000 16 010000 16 01ffff 16 01ffff 16 01ffff 16 ffffff 16 ffffff 16 ffffff 16 ffffff 16 00ffff 16 010000 16 00ffff 16 010000 16 00ffff 16 010000 16 00ffff 16 (ml 2 , ml 1 , ml 0 ) = (0, 0, 0) rom size : 124 kbytes (ml 2 , ml 1 , ml 0 ) = (0, 0, 1) rom size :120 kbytes (ml 2 , ml 1 , ml 0 ) = (1, 1, 0) rom size : 96 kbytes (ml 2 , ml 1 , ml 0 ) = (1, 1, 1) rom size : 32 kbytes : external memory area note . in the external bus mode b, bank 10 16 Cff 16 cannot be accessed. previous version
(3) revision description list M37736MHBXXXGP datasheet fig. 73 memory allocation (modification of internal rom and ram area by memory allocation selection bits) internal ram 3968 bytes internal ram 3968 bytes internal ram 2048 bytes sfr sfr sfr (4 kbytes) (1.9 kbytes) internal rom 120 kbytes internal rom 124 kbytes internal rom 60 kbytes 000000 16 00007f 16 000080 16 000fff 16 000000 16 00007f 16 000080 16 000fff 16 002000 16 000000 16 00007f 16 000080 16 00087f 16 001000 16 001000 16 010000 16 01ffff 16 01ffff 16 ffffff 16 ffffff 16 ffffff 16 00ffff 16 010000 16 00ffff 16 010000 16 00ffff 16 (ml 2 , ml 1 , ml 0 ) = (0, 0, 0) (ml 2 , ml 1 , ml 0 ) = (0, 0, 1) (ml 2 , ml 1 , ml 0 ) = (0, 1, 0) : external memory area internal ram 2048 bytes internal ram 2048 bytes internal ram 3968 bytes sfr sfr sfr (45.9 kbytes) (28 kbytes) internal rom 16 kbytes internal rom 32 kbytes internal rom 96 kbytes 000000 16 00007f 16 000080 16 00087f 16 000000 16 00007f 16 000080 16 00087f 16 00c000 16 000000 16 00007f 16 000080 16 000fff 16 008000 16 008000 16 010000 16 ffffff 16 ffffff 16 ffffff 16 00ffff 16 010000 16 00ffff 16 010000 16 00ffff 16 (ml 2 , ml 1 , ml 0 ) = (1, 0, 0) (ml 2 , ml 1 , ml 0 ) = (1, 0, 1) (ml 2 , ml 1 , ml 0 ) = (1, 1, 0) (29.9 kbytes) 01ffff 16 note . in the external bus mode b, bank 10 16 Cff 16 cannot be accessed. revised version
page p67 table 12 p90 [external bus mode b] rev. rev. no. date 2.00 980731 revision description list M37736MHBXXXGP datasheet (4) revision description previous version memory allocation selection bits internal rom area ml 2 0 0 1 1 ml 1 0 0 1 1 ml 0 0 1 0 1 001000 16 ?01ffff 16 002000 16 ?01ffff 16 008000 16 ?01ffff 16 008000 16 ?00ffff 16 cs 0 access address 001000 16 ?001fff 16 001000 16 ?007fff 16 001000 16 ?007fff 16 cs 1 020000 16 ?03ffff 16 020000 16 ?03ffff 16 020000 16 ?03ffff 16 010000 16 ?03ffff 16 memory allocation selection bits internal rom area ml 2 0 0 0 1 1 1 ml 1 0 0 1 0 0 1 ml 0 0 1 0 0 1 0 001000 16 ?01ffff 16 002000 16 ?01ffff 16 001000 16 ?00ffff 16 008000 16 ?00ffff 16 00c000 16 ?00ffff 16 008000 16 ?01ffff 16 cs 0 access address 001000 16 ?001fff 16 000880 16 ?000fff 16 000880 16 ?007fff 16 000880 16 ?007fff 16 001000 16 ?007fff 16 cs 1 020000 16 ?03ffff 16 020000 16 ?03ffff 16 010000 16 ?03ffff 16 010000 16 ?03ffff 16 008000 16 ?00bfff 16 010000 16 ?03ffff 16 020000 16 ?03ffff 16 revised version previous version revised version [external bus mode b] memory expansion mode and microprocessor mode (wait 0 : the external memory area is accessed when wait bit = 0 and wait selection bit = 1.) [external bus mode b] memory expansion mode and microprocessor mode (wait 0 : the external memory area is accessed when wait bit = 0 and wait selection bit = 0.)

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